Found 903 jobs on 91 pages

31 Oct
PLL/Clocking Design Engineer
Location: San Diego, CA
Salary: N/A

and Modeling: Skilled in developing System Verilog models, and performing behavioral simulations to explore new architectural...

31 Oct
Senior Principal Electronics Engineer
Location: Torrance, CA
Salary: N/A

for microcontrollers and/or VHDL/Verilog for firmware. Distingued record of creativity and innovation recognized as an autorhity...

31 Oct

verification. Proficient experience with Verilog, System Verilog, Python/Perl/TCL/Shell scripting, C/C++, System C and industry...

31 Oct
Principal Design Verification Engineer
Location: Edinburgh - Freer, TX
Salary: N/A

and experience of Verilog and System Verilog Excellent debug and problem-solving skills. Has experience with both IP and SOC level...; Experience in Power aware simulations or Formal Verification is a big plus Experience in Verilog-AMS, analog behavior modelling...

31 Oct
Senior FPGA Engineer
Location: Herndon, VA
Salary: N/A

architectures Implementing and documenting FPGA designs using HDL (System Verilog, VHDL, etc.) Supporting system integration...+ years of related experience FPGA design experience using Verilog/System Verilog or VHDL languages targeting Xilinx/Altera...

31 Oct
Electrical Engineer II
Location: Arden Hills, MN
Salary: N/A

Familiarity with C# creating GUI’s and test applications Experience with Altium, Verilog, VHDL, and/or SolidWorks Requisition...

30 Oct
Senior Analog Mixed Signal Verification Engineer
Location: Richardson, TX
Salary: N/A

System Verilog (or equivalent) models, test benches, and automated verification simulations for mixed signal circuit blocks...

30 Oct
Sr.Staff SoC Lead design verification Engineer
Location: Santa Clara, CA
Salary: N/A

Verilog assertions, and performance. Strong System Verilog / UVM based verification skills, experience with assertions...

30 Oct
Design Engineer Intern
Location: San Jose, CA
Salary: N/A

. MS or PhD level program enrollment Background in RTL design including Verilog, synthesis, lint, formal...

30 Oct
CPU RTL Engineer
Location: Austin, TX
Salary: N/A

, and power Minimum Qualifications Minimum Qualifications Minimum BS Knowledge of Verilog or VHDL Experience...