Found 903 jobs on 91 pages

01 Nov
Principal Electrical Engineer Tech
Location: Hunt Valley, MD
Salary: N/A

community. Experience with FPGA design in VHDL or Verilog is a bonus. This position requires that the candidate be a US citizen...

01 Nov
Graphics (GPU) Design Verification Engineer
Location: Austin, TX
Salary: N/A

Object Oriented programming language Experience with Verilog or other HDLs Key Qualifications Key Qualifications...

01 Nov
Wireless SoC Design Engineer
Location: Sunnyvale, CA
Salary: N/A

with the ASIC design flow. Knowledge of digital design, SoC architecture, and HDL languages like Verilog. Key...

01 Nov
Graphics (GPU) Design Verification Engineer
Location: Austin, TX
Salary: N/A

architectures, or equivalently complex IPs Experience developing Object Oriented infrastructure in System Verilog or C...

01 Nov
PCIe SOC RTL Design Lead
Location: San Jose, CA
Salary: N/A

and proven experience of RTL design, Verilog and System Verilog Deep knowledge of front-end tools (Verilog simulators, linters...

01 Nov
Graphics (GPU) Performance Analysis Engineer
Location: Orlando, FL
Salary: N/A

Experience in computer architecture. Experience with Verilog, C and C++. Experience with scripting language Python. Minimum BS...

01 Nov
ASIC Engineering Technical Leader
Location: San Jose, CA
Salary: N/A

with primary focus on RTL Design. Create micro-architecture specifications and participate in reviews Implement Verilog RTL... Prior experience with Verilog/System Verilog Prior experience with Clock Domain, Reset Domain Crossing issues, and Low...

01 Nov
ASIC/SoC Design Verification Engineer
Location: Fremont, CA
Salary: N/A

for function/performance verification.Proficient experience with Verilog, System Verilog, Python/Perl/TCL/Shell scripting, C/C...

01 Nov
ASIC Design Verification Engineer
Location: San Jose, CA
Salary: N/A

and functional coverage Minimum Qualifications: Prior experience with System Verilog and UVM methodology Prior experience... on experience with System Verilog constraints, structures and classes. Prior experience with functional coverage and constrained...

31 Oct
PLL/Clocking Design Engineer
Location: Cupertino, CA
Salary: N/A

and Modeling: Skilled in developing System Verilog models, and performing behavioral simulations to explore new architectural...