Found 903 jobs on 91 pages

31 Oct
PLL/Clocking Design Engineer
Location: Austin, TX
Salary: N/A

and Modeling: Skilled in developing System Verilog models, and performing behavioral simulations to explore new architectural...

31 Oct
Battery Management System Electrical Engineer
Location: San Diego, CA
Salary: N/A

and calculations to verify its conformance to the requirements. (PSPICE, ANSYS, Verilog or equivalent) - Conduct design validation...

31 Oct
FE Design and Timing Analysis Integration Engineer
Location: Sunnyvale, CA
Salary: N/A

. Knowledge of basic SoC Architecture and HDL languages like Verilog to collaborate with our logic design team for timing fixes...

31 Oct

& environments is essential. Expert in coding with Verilog/VHDL/SystemVerilog, UVM, PSL/SVA is mandatory. Experience...

31 Oct
Battery Management System Electrical Engineer
Location: San Diego, CA
Salary: N/A

and calculations to verify its conformance to the requirements. (PSPICE, ANSYS, Verilog or equivalent) - Conduct design validation...

31 Oct
Eng Sr - Elec
Location: San Diego, CA
Salary: N/A

(preferred) or ASIC Design / Development VHDL (preferred) or Verilog HDL coding Experience with digital design tools... and timing closure Experience with clock domain crossing techniques Experience with designer-level test bench (VHDL, Verilog...

31 Oct
PLL/Clocking Design Engineer
Location: San Diego, CA
Salary: N/A

and Modeling: Skilled in developing System Verilog models, and performing behavioral simulations to explore new architectural...

31 Oct
PLL/Clocking Design Engineer
Location: Austin, TX
Salary: N/A

and Modeling: Skilled in developing System Verilog models, and performing behavioral simulations to explore new architectural...

31 Oct
Sr Firmware Engineer/Electrical Engineer
Location: Moorestown, NJ
Salary: N/A

skills Simulation/Testbench experience with higher level chip scenarios with Questa-Sim System Verilog knowledge...

31 Oct
PLL/Clocking Design Engineer
Location: Cupertino, CA
Salary: N/A

and Modeling: Skilled in developing System Verilog models, and performing behavioral simulations to explore new architectural...