Found 811 jobs on 82 pages

02 May
Senior Digital Integration & Timing Engineer
Location: San Diego, CA
Salary: N/A

) with functional ECOs in the mix. Familiarity with DFT and backend related methodologies and tools. Proficient with RTL Verilog/VHDL...

02 May
Digital Integration & Timing Engineer
Location: San Diego, CA
Salary: $52.99 - 79.76 per hour

. Familiarity with DFT and backend related methodologies and tools. Proficient with RTL Verilog/VHDL. Knowledge of digital top...

02 May
Standard Cell Design Methodology & Flow Engineer
Location: Santa Clara, CA
Salary: N/A

of Verilog/SystemVerilog, UDPs, Verilog simulation and formal verification Exposure to Design For Test, scan concept and write... sophisticated digital block in Verilog/SystemVerilog, run simulations or formal check for verification. - Use data analysis...

02 May
ASIC Design Engineer - Neural Engine DMA
Location: Cupertino, CA
Salary: N/A

SoC front-end ASIC RTL digital logic design using Verilog or System Verilog. Experience working multi-functionally...

02 May
Senior Digital Integration & Timing Engineer
Location: Sunnyvale, CA
Salary: N/A

) with functional ECOs in the mix. Familiarity with DFT and backend related methodologies and tools. Proficient with RTL Verilog/VHDL...

02 May
Principal Design Verification Engineer - PCIe
Location: Austin, TX
Salary: N/A

. AMBA5 CHI, AMBA4 ACE or AXI). Previous experience in specification, creation, and debug of System Verilog/UVM constrained...

02 May
Semiconductor Design Engineer
Location: San Jose, CA
Salary: $126984 - 154000 per year

. Develop NAND Verilog models for internal/external customers. Employer will accept a Master's degree in Electrical...

02 May
Senior Staff Design Verification Engineer
Location: Austin, TX
Salary: $139100 - 205790 per year

constrained-random verification test environment using Verilog/System Verilog, UVM and C programming, including testbenches... of behavioral coding in verilog and SystemVerilog Experience programming in C or C++ and in scripting using Python, PERL or Bash...

02 May
Digital Integration & Timing Engineer
Location: San Diego, CA
Salary: N/A

) with functional ECOs in the mix. Familiarity with DFT and backend related methodologies and tools. Proficient with RTL Verilog/VHDL...

02 May
Digital Integration & Timing Engineer
Location: Sunnyvale, CA
Salary: N/A

) with functional ECOs in the mix. Familiarity with DFT and backend related methodologies and tools. Proficient with RTL Verilog/VHDL...