Found 903 jobs on 91 pages

31 Oct
Analog IC Design Engineer, Staff
Location: Irvine, CA
Salary: $107300 - 158840 per year

design CAD tools such as Spectre, Spice, Matlab, Hsim, Verilog, etc. Lab testing skills to evaluate the prototype unit...

31 Oct
Eng Sr Prin - Elec
Location: San Diego, CA
Salary: N/A

(preferred) or Verilog HDL coding Familiarity with Xilinx Vivado or Intel/Altera Quartus Experience with internal logic...

31 Oct
PLL/Clocking Design Engineer
Location: Austin, TX
Salary: N/A

and Modeling: Skilled in developing System Verilog models, and performing behavioral simulations to explore new architectural...

31 Oct
Electrical Engineer II
Location: Arden Hills, MN
Salary: N/A

Familiarity with C# creating GUI's and test applications Experience with Altium, Verilog, VHDL, and/or SolidWorks Requisition...

31 Oct
PLL/Clocking Design Engineer
Location: San Diego, CA
Salary: $115700 - 174200 per year

and Modeling: Skilled in developing System Verilog models, and performing behavioral simulations to explore new architectural...

31 Oct
PLL/Clocking Design Engineer
Location: Cupertino, CA
Salary: $121900 - 183600 per year

and Modeling: Skilled in developing System Verilog models, and performing behavioral simulations to explore new architectural...

31 Oct
Eng Sr Prin - Elec
Location: Austin, TX
Salary: N/A

(preferred) or Verilog HDL coding Familiarity with Xilinx Vivado or Intel/Altera Quartus Experience with internal logic...

31 Oct
FE Design and Timing Analysis Engineer
Location: Sunnyvale, CA
Salary: N/A

. Knowledge of basic SoC Architecture and HDL languages like Verilog / System Verilog to collaborate with our logic design team...

31 Oct
Principal Engineer, Analog Design Engineering
Location: Edinburgh - Freer, TX
Salary: N/A

(Virtuoso ADE Spectre) Scripting languages (Shell, TCL, PERL, Python) HDL programming languages (Verilog / SystemVerilog...) Analog Behavioral Models (Verilog-A, Verilog-AMS, Wreal, SystemVerilog, EEnet) Mixed-Signal Verification methodology...

31 Oct
Eng Sr - Elec
Location: Austin, TX
Salary: N/A

(preferred) or ASIC Design / Development VHDL (preferred) or Verilog HDL coding Experience with digital design tools... and timing closure Experience with clock domain crossing techniques Experience with designer-level test bench (VHDL, Verilog...