Found 614 jobs on 62 pages

26 Jun
Senior Staff Engineer -FPGA Design & Verification
Location: Bangalore, Karnataka
Salary: N/A

or PCDDR System Verilog & UVM ARM CPU and SoC architectures (ADI/AMBA / ARM v8 etc) Validation and debug of digital...

26 Jun
Emulation Engineer
Location: Noida, Uttar Pradesh
Salary: N/A

, XILINX ISE, Work experience in Xilinx FPGA based design implementation. FPGA RTL coding(Verilog/VHDL/System Verilog...

26 Jun
Senior/Staff Verification Engineer
Location: Bangalore, Karnataka
Salary: N/A

architecture Deep understanding of digital design concepts and Verilog/VHDL coding Good in logical programming using C/C...

26 Jun
CPU Timing Engineer -- Staff Engineer
Location: Hyderabad, Telangana
Salary: N/A

noise, cross-talk and others. Knowledge of basic SoC architecture and HDL languages like Verilog. Applicants...

26 Jun
Lead Software Engineer
Location: Noida, Uttar Pradesh
Salary: N/A

knowledge of ASIC design flows, Verification, Digital Logic, Synthesis, RTL to GDS flow expertise, HDL Languages Verilog/VHDL/SV...

26 Jun
Senior Manager, ASIC Verification
Location: Hyderabad, Telangana
Salary: N/A

with RTL debugging, score boarding and code coverage analysis Sound knowledge of Verilog and System Verilog languages... Exposure to modelling and validating complex analog circuits in Verilog and Verilog-A Experience of complex mixed signal...

26 Jun
Engineer - Memory Circuit Design Verification
Location: Hyderabad, Telangana
Salary: N/A

(Primesim/Finesim) or Verilog (Xcelium/VCS) based verification. Guide and set the direction for the verification effort...

26 Jun
Staff Engineer
Location: Vadodara, Gujarat
Salary: N/A

/ Verilog / System Verilog. Strong Basics of Digital design Experience of working with Analog Mixed Signal design team...

26 Jun
Staff Engineer, Verification Engineering
Location: Bangalore, Karnataka
Salary: N/A

architectures. Hands on experience in developing, updating and debugging of Verilog, SV-UVM , SOC level testbenches... transaction level modeling, pseudo and constrained random techniques with System Verilog In-depth knowledge of SV-UVM...

26 Jun
Staff Engineer Memory Design
Location: Hyderabad, Telangana
Salary: N/A

in Finesim and/or Hspice Experience with power network analysis Extensive knowledge in verilog modeling and simulation...