Found 842 jobs on 85 pages

20 Mar
Design Integration Engineer
Location: Irvine, CA
Salary: N/A

. Knowledge of basic SoC Architecture and HDL languages like Verilog to collaborate with our logic design team for timing fixes...

20 Mar
Digital Signal Processing (DSP) Software Engineering Scientist
Location: USA
Salary: $104000 - 174000 per year

. Demonstrated experience with any of the following: Verilog/VHDL, Python, Matplotlib, C++. Experience implementing DSP algorithms...

20 Mar
Design Integration Engineer
Location: San Diego, CA
Salary: N/A

. Knowledge of basic SoC Architecture and HDL languages like Verilog to collaborate with our logic design team for timing fixes...

20 Mar
Design Integration Engineer
Location: Sunnyvale, CA
Salary: N/A

. Knowledge of basic SoC Architecture and HDL languages like Verilog to collaborate with our logic design team for timing fixes...

19 Mar
Electrical Propulsion & Power Systems Engineer
Location: Centre County, PA
Salary: $109300 - 191000 per year

(Aerovironment, Arbin) Experience with embedded C/C++ and VHDL/Verilog firmware languages Your working location will be fully...

17 Mar
Spacecraft FPGA Design Engineer
Location: Potomac, MD
Salary: N/A

(Verilog or VHDL) languages. Proficient with radiation hardened FPGA tool flows. Proficient in design of FPGA architecture...

17 Mar
Embedded Software Engineer
Location: Seattle, WA
Salary: N/A

generation. Experience with Linux kernel module development Experience with FPGA development (Verilog, VHDL, etc.), especially...

17 Mar
Sr. SOC Verification Engineer
Location: San Diego, CA
Salary: N/A

verification experience. Expertise in HVL and HDL (SystemVerilog, Verilog). Advanced knowledge of HVL methodology (UVM/OVM/VMM... verification framework Knowledge of industry standard interfaces. Experience with System Verilog Assertion (SVA) Programing...

17 Mar
SOC Verification Engineer
Location: San Diego, CA
Salary: N/A

of verification experience. Solid fundamentals in Verilog and System Verilog for verification. Basic knowledge of UVM methodology... of System Verilog Assertion (SVA) Programing experience in C Experience writing scripts in languages such as Perl or Python...

17 Mar
Design Integration Engineer
Location: Sunnyvale, CA
Salary: N/A

. Knowledge of basic SoC Architecture and HDL languages like Verilog to collaborate with our logic design team for timing fixes...