Found 903 jobs on 91 pages

18 Oct
Mixed-Signal IP Firmware Engineer
Location: Cupertino, CA
Salary: N/A

knowledge of RTL design. Deep knowledge of Verilog and SystemVerilog. Experience with version control tools (git, Perforce...

18 Oct
RTL Design Engineer
Location: Austin, TX
Salary: N/A

knowledge of Verilog and System-Verilog Experience with front-end tools (Verilog simulators, linters, clock-domain crossing... checkers) Working knowledge of synthesis, static timing, DFT is a huge plus Some working experience with System-Verilog...

18 Oct
Mixed-Signal IP Firmware Engineer
Location: Cary, NC
Salary: N/A

of RTL design. Deep knowledge of Verilog and SystemVerilog. Experience with version control tools (git, Perforce...

18 Oct
Senior Electrical Engineer
Location: Marlborough, MA
Salary: N/A

/Programming: MATLAB, Simulink, C++, PADs, Altium Designer, OrCad, Verilog HDL/VHDL, LabVIEW, Multisim, Intel-Quartus, SolidWorks...

18 Oct
Senior Electrical Engineer
Location: Marlborough, MA
Salary: N/A

/Programming: MATLAB, Simulink, C++, PADs, Altium Designer, OrCad, Verilog HDL/VHDL, LabVIEW, Multisim, Intel-Quartus, SolidWorks...

17 Oct
Summer Intern, Foundry
Location: San Jose, CA
Salary: N/A

experience. RTL design using Verilog HDL is preferred. Good trouble-shooting skills. Education Requirements: BS...

17 Oct
Timing Design Engineer
Location: Cupertino, CA
Salary: N/A

Verification Working Knowledge of Basic SoC Architecture and HDL languages like Verilog to be able with logic design team...

17 Oct
Analog/Mixed-Signal Circuit Design Engineer
Location: Austin, TX
Salary: N/A

, developing System Verilog models, and performing behavioral simulations to explore new architectural performance and functions...

17 Oct
FPGA Design Engineer
Location: Tucson, AZ
Salary: N/A

applications. With expertise in FPGA system development and VHDL/Verilog module design, the successful candidate will optimize... and develop digital systems on FPGA. Drive FPGA top level integration, floor planning and timing closure. Integrate VHDL/Verilog...

17 Oct
RTL Design Engineer
Location: Cupertino, CA
Salary: N/A

, RTL design, Verilog and SystemVerilog Deep knowledge of front-end tools (Verilog simulators, linters, clock-domain...