Found 898 jobs on 90 pages

07 Nov
UVM Design Verification Engineer III
Location: Wilmington, MA
Salary: N/A

-on ASIC designs · Develop test benches for FPGA or ASIC design verification using UVM, System Verilog, Verilog or VHDL... and/or ASIC verification design · Experience in UVM, System Verilog, C and scripting languages · Experience with Verilog...

07 Nov
Senior Staff Analog Mixed Signal IC Design Engineer
Location: Santa Clara, CA
Salary: $128160 - 192000 per year

and analytical skills. Strong knowledge on IC design CAD tools such as Spectre, Spice, Matlab, Hsim, Verilog, etc. Strong team...

07 Nov
ASIC Design Verification Engineer
Location: San Jose, CA
Salary: N/A

dynamic market using industry proven methodologies using System Verilog and UVM. You can become a member of an extremely... with SV and UVM, well versed in OOP Tools/Languages: System Verilog (TB structures - Class, SVA, etc.), UVM, VCS, Incisive...

07 Nov
Design Verification Engineer
Location: San Jose, CA
Salary: $107000 - 171000 per year

Verilog assertions and ability to quickly write effective coverage and assertion properties. Ability to understand Verilog... for design IPs or VIPs. Expertise in System Verilog especially writing SVAs for formal. Familiar with verification methodologies...

07 Nov
UVM Design Verification Engineer III
Location: Wilmington, MA
Salary: N/A

-on ASIC designs · Develop test benches for FPGA or ASIC design verification using UVM, System Verilog, Verilog or VHDL... and/or ASIC verification design · Experience in UVM, System Verilog, C and scripting languages · Experience with Verilog...

07 Nov
RTL Design Engineer
Location: Beaverton, OR
Salary: N/A

experience of RTL design, Verilog and SystemVerilog Deep knowledge of front-end tools (Verilog simulators, linters, clock-domain...

07 Nov

of Analog Mixed Signal verification experience utilizing System Verilog Preferred qualifications: Experience using Verilog..., SystemVerilog, Verilog-A, Verilog-AMS, Python, UVM, Cadence ADE-L/ADE-XL or Maestro Strong background with EDA design tools...

07 Nov
Senior Digital ASIC Verification Engineer
Location: New York City, NY
Salary: $115500 - 184500 per year

to your architectural functional block using System Verilog UVM and/or C where applicable You will perform coverage driven verification...

07 Nov
Senior Test and Integration Engineer
Location: Linthicum, MD
Salary: N/A

, Python, C/C++, RISC Assembly, Bash, Tcl/TK, and Verilog. Ten (10+) years of experience with GitLab, FPGA design, Xilinx...

07 Nov
Principal Analog Mixed Signal IC Design Engineer
Location: Santa Clara, CA
Salary: $144180 - 216000 per year

, Verilog, etc. ·Lab testing skills to evaluate the prototype unit to the design specification. ·Completed a BS/MS/PhD degree...