Found 899 jobs on 90 pages

04 Jul
Senior Test and Integration Engineer
Location: Linthicum, MD
Salary: N/A

, Python, C/C++, RISC Assembly, Bash, Tcl/TK, and Verilog. Ten (10+) years of experience with GitLab, FPGA design, Xilinx...

03 Jul
Optical DSP System Engineer
Location: Alpharetta, GA
Salary: N/A

. Demonstrated experience with SystemC, CatapultC, or Verilog is strongly preferred. If you do not have this experience a willingness...

03 Jul
Senior Design Engineer, Coherent High Speed Interconnect
Location: Santa Clara, CA
Salary: N/A

optimization. Strong working knowledge of Verilog or System Verilog. Good communication skills and interpersonal skills...

03 Jul
ASIC Design Engineer - New College Grad 2024
Location: Santa Clara, CA
Salary: N/A

performance semiconductor designs. Verilog expertise required as is a deep understanding of ASIC design flow including RTL...

03 Jul
FPGA Engineer
Location: Linthicum Heights, MD
Salary: N/A

is a plus). Demonstrated expertise in the development of HDL modules using Verilog/SystemVerilog or VHDL (SystemVerilog preferred). Expert... to at least read and write both VHDL and Verilog/SystemVerilog at a basic level. Proven ability to implement complex algorithms in...

03 Jul
Principal Design Engineer
Location: Austin, TX
Salary: N/A

Verilog, synthesis, lint, formal Strong communication skills Scripting language experience a plus We’re doing work...

03 Jul
FPGA Electrical Engineer
Location: Chicago, IL
Salary: N/A

), network protocols. – Excellent knowledge of Verilog. – Proficiency with VHDL and System Verilog. – Proficiency with a full... financial services industry is a plus. Keywords: Chicago IL Jobs, FPGA Electrical Engineer, FPGA, VHDL, Verilog, Vivado...

02 Jul
Senior/Staff Design Verification Engineer - Austin, TX
Location: Austin, TX
Salary: $150000 - 200000 per year

and debug RTL designs using Verilog and SystemVerilog. Improve and refine verification processes, methodologies, and metrics... using scripting languages such as Shell scripts, Python, and JavaScript Strong skills in debugging RTL (Verilog) and UVM/C...

01 Jul
Senior Digital IC Design Engineer - Power Management
Location: Bloomington, MN
Salary: N/A

development, RTL description using System Verilog, Verilog Simulation Verification via developed Test Benches, Logic Synthesis..., both by manual development and automated generation Create Cadence schematic database of Digital Blocks via Virtuoso System Verilog...