Found 6285 jobs on 629 pages

20 Dec
High Speed Circuit & System Architect
Location: San Jose, CA
Salary: N/A

. Preferred Knowledge/Skill/Abilities: Able to create IBIS-AMI model. Can code in System-Verilog. Fluent in verbal and written...

20 Dec

concepts, techniques, and course work Basic knowledge of HDL/HVLs (e.g. VHDL, Verilog, System Verilog, UVM) and programming...

20 Dec
Product Engineer
Location: Hillsboro, OR
Salary: N/A

in hardware description languages (HDL) such as Verilog or VHDL is required. Experience in the use of programmable logic devices...

20 Dec
Principal Analog/Mixed-Signal Verification Engineer
Location: San Jose, CA
Salary: N/A

links, and wireless transmission systems. Hands-on in modeling and simulating with System-Verilog (WREAL), Verilog-AMS...: Able to create IBIS-AMI model. Can code in System-Verilog (WREAL). Fluent in verbal and written communications...

20 Dec
Adjunct Faculty - Engineering
Location: Holyoke, MA
Salary: N/A

); Introduction to Electronic Digital Circuits with Verilog (On-Campus or Online) Under the direction of the Academic Department...

20 Dec
Principal FPGA Electrical Design Engineer - Onsite Marlborough/Tewksbury, MA
Location: Tewksbury, MA
Salary: $96000 - 200000 per year

of professional experience designing FPGAs using VHDL/Verilog (an advanced degree in a related field may be substituted for two...

20 Dec
Electrical Engineering Co-op- Summer 2025
Location: Cincinnati, OH
Salary: N/A

such as coding in C/C++, VHDL, Verilog, and with peripherals such as Ethernet, USB, and busses such as I2C and SPI Coding in LabVIEW...

20 Dec

designing FPGAs using VHDL/Verilog (an advanced degree in a related field may be substituted for two additional years...

20 Dec
Senior FPGA Electrical Design Engineer - Onsite Tewksbury/Marlborough, MA
Location: Marlborough, MA
Salary: $77000 - 163000 per year

of professional experience designing FPGAs using VHDL/Verilog (an advanced degree in a related field may be substituted for two...

20 Dec
CPU Physical Design Engineer
Location: Santa Clara, CA
Salary: N/A

sizing. Perform feasibilities to validate implementability, area, timing and power. Synthesize the Verilog RTL into gate...