Found 861 jobs on 87 pages

21 Sep
ASIC & FPGA Design Engineering
Location: Orlando, FL
Salary: N/A

will be to develop System Verilog source code and simulation for safety electronic device application. Candidate will operate... as well as externally to customers and suppliers. Excellent oral and written communications skills are a must. Hard Skills Verilog...

21 Sep
Senior Formal Verification Engineer
Location: Austin, TX
Salary: N/A

Verilog and UVM methodology expertise Must have 5+ years of experience and BSEE, MSEE preferred #FormalVerification #UVM...

21 Sep
FPGA Developer
Location: Boise, ID
Salary: N/A

experience with a strong body of work in VHDL or Verilog development Fluent in VHDL or Verilog hardware description languages...

21 Sep
Eng Sr Prin - Sys
Location: Rome, NY
Salary: N/A

Knowledge of hardware design principles, testing tools, equipment, and techniques Familiarity with Verilog/VHDL and FPGA...

21 Sep
Electrical Engineer II
Location: Middletown, RI
Salary: N/A

, verilog, vhdl, maritime, navy, defense Top Skills Details: Design,PCB,Electrical Engineering,Mixed Signal Additional...

21 Sep
FPGA Engineer
Location: Kirkland, WA
Salary: N/A

schedule. Job functions would include: Design complex logic in both Verilog and VHDL (Verilog currently is the primary HDL... programming FPGAs with Verilog and/or VHDL Mastery of Xilinx constraints language and concepts Mastery of Xilinx debugging tools...

21 Sep
ASIC Engineer - Infra Silicon Enablement
Location: Menlo Park, CA
Salary: N/A

applications like Video, AI/ML and Networking. Experience with Verilog/System Verilog preferred Experience with Linux systems...

21 Sep
Digital Engineer I/II
Location: San Diego, CA
Salary: $81000 - 132000 per year

years of related experience coding VHDL/Verilog using Xilinx Vavado or Intel Quartus development software. Two years...

21 Sep
Senior Formal Verification Engineer
Location: Hillsboro, OR
Salary: N/A

Verilog and UVM methodology expertise Must have 5+ years of experience and BSEE, MSEE preferred #FormalVerification #UVM...

21 Sep
Senior Formal Verification Engineer
Location: Fort Collins, CO
Salary: N/A

Verilog and UVM methodology expertise Must have 5+ years of experience and BSEE, MSEE preferred #FormalVerification #UVM...