Found 910 jobs on 91 pages

25 Oct
Analog Mixed Signal Circuit Design Intern - PhD
Location: Santa Clara, CA
Salary: $26 - 52 per hour

(e.g. Verilog, VerilogAMS, System Verilog), high-level languages (e.g., C, C++, Matlab) and scripting languages (e.g Python...

25 Oct
CPU Senior Design Verification Engineer
Location: Santa Clara, CA
Salary: N/A

with modern processor micro-architectures Experience with RTL languages like VHDL/Verilog Familiarity with SystemVerilog...

25 Oct
Mixed Signal Modeling/Verification Engineer
Location: Austin, TX
Salary: N/A

-leading SoCs. Description Description Development of RNM RF/Analog models in System Verilog. Develop models with self...

25 Oct
ASIC Engineer, Infra Silicon
Location: Menlo Park, CA
Salary: N/A

and Networking designs Experience in Python, C/C++ (data structures, algorithms, and OOP) or Verilog/System Verilog Experience...

25 Oct
Senior SOC Design Engineer
Location: Santa Clara, CA
Salary: N/A

(Verilog), verification (UVM, System Verilog), System-On-Chip design/integration flow, and design automation. Strong coding...

25 Oct

Verilog and UVM. Ability to write tests using UVM. Experience with writing assertions and coverage monitors using SVA...

25 Oct
Electrical Engineer
Location: Oak Ridge, TN
Salary: N/A

programming using Verilog (SystemVerilog or VHDL will be considered). Simulation using ModelSim PCB bring-up/debugging...

25 Oct
Design Verification Engineer (eInfochips Inc)
Location: San Jose, CA
Salary: N/A

along-with complex SoC debug is must At-least 10+ years of experience in System Verilog HVL and C/C++. At-least 10+ year of experience...

25 Oct
Eng Prin - Elec
Location: Hudson, NH
Salary: N/A

, Verilog) Strong "hands on" laboratory experience with instrumentation, processes, and equipment (including Low Noise...

25 Oct
Mixed Signal Modeling/Verification Engineer
Location: Austin, TX
Salary: N/A

-leading SoCs. Description Description Development of RNM RF/Analog models in System Verilog. Develop models with self... concepts/topologies. Familiarity with basic logic building blocks and HDL language like verilog. BSEE required. Key...