Found 51 jobs on 6 pages

02 May
Sr. Program Manager
Location: Pulau Pinang
Salary: N/A

verification flow Proficient with Verilog, System Verilog and UVM. * Proficient in UVM concepts and SystemVerilog language. (SVA...

30 Apr
SoC Design Engineer (DFT)
Location: Malaysia
Salary: N/A

). Familiar with verilog, system verilog and Perl/Tcl script. Knowledge in advance DFT methodology including ATPG, MBIST, JTAG...

30 Apr
CPU System Validation Engineer
Location: Malaysia
Salary: N/A

verification e.g. System Verilog, RTL simulation. Experience in x86/ARM/RISC-V CPU architecture. Proficient in C/C++ , assembly...

30 Apr
Senior Digital Design Engineer (MNC Semiconductor)
Location: Pulau Pinang
Salary: N/A

level Verilog test bench for verification. Give guidance to fresh digital design engineers. Scripting skills is an advantage...

28 Apr
MTS Silicon Design Engineer (FEINT)
Location: Pulau Pinang
Salary: N/A

with RTL designer and PD team. PREFERRED EXPERIENCE: Experience with Verilog RTL design/implementation and has experience...

28 Apr
SOC Design Engineer
Location: Bayan Lepas, Pulau Pinang
Salary: N/A

development. Ø Rich experience with Verilog, familiar with more than one script language (shell, TCL, Perl, python are acceptable...

27 Apr
Silicon Design Graduate Trainee (Design)
Location: Pulau Pinang
Salary: N/A

improvement. PREFERRED EXPERIENCE: Exposure to System Verilog, Verilog , Perl, TCL, Python and of course AI/ML...

27 Apr
MTS Silicon Design Engineer(Verification)
Location: Pulau Pinang
Salary: N/A

and Windows environments. Strong background with UVM, Verilog, System Verilog, C, and C++ USB,UFS,Ethernet,PCIE,AXI knowledge...

27 Apr
SMTS Silicon Design Engineer(Verification)
Location: Pulau Pinang
Salary: N/A

. Strong background with UVM, Verilog, System Verilog, C, and C++ USB,UFS,Ethernet,PCIE,AXI knowledge is a plus Developing UVM based...

26 Apr
SOC Design Engineer
Location: Bayan Lepas, Pulau Pinang
Salary: N/A

experience. Ø Understand the front-end and back-end processes of chip development. Ø Rich experience with Verilog, familiar...