Found 861 jobs on 87 pages

25 Sep
Software Developer - Advanced Computing Lab
Location: Pittsburgh, PA
Salary: N/A

chance to work with modern software languages such as Python and C/C++, and hardware design languages including Verilog, VHDL...

24 Sep
INFO SECURITY ANALYST IV - FIPS 140
Location: Columbia, MD
Salary: $75 - 80 per hour

) and development environments. Nice to Have: Experience with VHDL and Verilog languages. Experience with debugging (GDB, Win DBG...

24 Sep
FPGA Engineer (Senior)
Location: Syracuse, NY
Salary: N/A

Description Language (VHDL)/Verilog Design and optimize high-performance digital circuits and systems using VHDL/Verilog while adhering... of experience in FPGA design and development or related experience Proficiency in VHDL/Verilog and familiarity with FPGA toolchains...

24 Sep
FPGA Engineer (Lead)
Location: Syracuse, NY
Salary: N/A

Description Language (VHDL)/Verilog Design and optimize high-performance digital circuits and systems using VHDL/Verilog while adhering... of experience in FPGA design and development or related experience Proficiency in VHDL/Verilog and familiarity with FPGA toolchains...

24 Sep
Digital Design Engineer
Location: San Diego, CA
Salary: $115000 - 165000 per year

, at a minimum, the knowledge, skills, and abilities listed here: Experience with VHDL/Verilog targeted to FPGA and/or ASIC platforms...

23 Sep
Electrical Engineer, Satellite Design (Senior, Principal)
Location: Falls Church, VA
Salary: N/A

and with integrating hardware and software systems is desired. Familiarity with FPGA programming (VHDL or Verilog) and Altera or Xilinx...

23 Sep
Senior Advanced ASIC FPGA Verification Engineer
Location: Scottsdale, AZ
Salary: N/A

or equivalent in a Linux Environment In-depth knowledge of System Verilog object oriented programming and the Universal... on concepts and ideas. Proficient with embedded micro-processing systems, FPGA Design and Verification using System Verilog...

22 Sep
Silicon Design Engineer
Location: San Jose, CA
Salary: N/A

are required: Position requires experience in the following: UVM programming; Verilog or System Verilog; C, C++, or Python; RTL Design...

22 Sep
Principal Logic Engineer
Location: Hillsboro, OR
Salary: $137600 per year

quality in Verilog Register Transfer Level (RTL). Interface with PHY vendor. Work closely with front end design and physical... Verilog. Ensure high quality of the design from the perspectives of functionality, timing, Clock Domain Crossing (CDC), Reset...

22 Sep
Mixed Signal IC Design Senior Engineer
Location: Goleta, CA
Salary: $85000 - 179000 per year

environments. Modelling experience with System Verilog/Real Modelling/Verilog AMS and coding synthesizable RTL. Experience in...