Found 13 jobs on 2 pages

28 Apr
FPGA / Embedded C/C++ Designer - Intel, Brno (až 85.000 Kč)
Location: Brno, Jihomoravský
Salary: 85000 per month

Engineering, Computer Engineering or relevant Experience in developing and implementing RTL for any FPGA platform (VHDL, Verilog..., System Verilog, OpenCL) Experience in programming in C/C++ Solid understanding of TCP/IP networks Knowledge of Linux...

27 Apr
Digital Engineering Intern
Location: Prague
Salary: N/A

English Basic knowledge of VHDL/Verilog The following skills would be considered a distinct advantage: Knowledge...

27 Apr
Digital Engineering Intern
Location: Prague
Salary: N/A

Communication skills in English Basic knowledge of VHDL/Verilog The following skills would be considered a distinct advantage...

26 Apr
FPGA / Embedded C/C++ Designer - Intel, Brno
Location: Brno, Jihomoravský
Salary: N/A

Engineering, Computer Engineering or relevant Experience in developing and implementing RTL for any FPGA platform (VHDL, Verilog..., System Verilog, OpenCL) Experience in programming in C/C++ Solid understanding of TCP/IP networks Knowledge of Linux...

21 Apr
Senior Digital Engineer
Location: Prague
Salary: N/A

– standard cells, IO cells, memory macros, PLLs, etc Perfect knowledge of Verilog/SystemVerilog or VHDL, Verilog/SystemVerilog...

20 Apr
Senior Digital Engineer
Location: Prague
Salary: N/A

of typical digital design components - standard cells, IO cells, memory macros, PLLs, etc Perfect knowledge of Verilog.../SystemVerilog or VHDL, Verilog/SystemVerilog preferred. Strong knowledge of UVM Experience with code coverage and functional...

18 Apr
FPGA programátoři
Location: Prague
Salary: 130000 per month

VHDL, Lattice, Verilog Máš zkušenosti s vývojem FPGA Xilinx ISE Skušenost s Vivado, Chipscope, ILA Domluvíš se anglicky...

15 Apr
Principal Verification Engineer
Location: Prague
Salary: N/A

simulation and regressions tools e.g. Cadence Incisive, vManager, IMC Familiar with either Verilog or VHDL RTL coding and ASIC...

15 Apr
FPGA programátoři
Location: Prague
Salary: N/A

jazyky VHDL, Lattice, Verilog Máš zkušenosti s vývojem FPGA Xilinx ISE Skušenost s Vivado, Chipscope, ILA Domluvíš...

22 Mar
Intern – Firmware Developer
Location: Brno, Jihomoravský
Salary: N/A

flow (VHDL/Verilog) and/or MCU design (C/C++). Ability to read electrical schematics is a plus. - Familiarity with Linux OS...