Found 9 jobs on 1 pages

19 Dec
IC hardware Validation Developer
Location: Leuven, Flemish Brabant
Salary: N/A

on interactions between different functions - Experience in VHDL/Verilog coding, simulation, synthesis for FPGA is an asset...

19 Dec
Digital ASIC Design and DSP Internship
Location: Leuven, Flemish Brabant
Salary: N/A

and written communication skills in English. Bonus points if you know Verilog/VHDL! ***Keysight is an Equal Opportunity...

15 Dec
Digital Design and Verification Engineer
Location: Brussels - Mechelen, Antwerp
Salary: N/A

. Interaction with IP department. Digital Modules RTL coding in synthesizable System-Verilog. Integration of modules in a top... with experience in HDL languages (Verilog, SystemVerilog). 5+ years of experience in digital design and/or verification with hands...

14 Dec
FPGA Engineer
Location: Liège
Salary: N/A

like PCIe, CoaXPress, DDR4, and Gigabit Ethernet. - Programming Languages: Proficiency in VHDL, Verilog, and Hardware...

22 Nov

MATLAB or Verilog A model of a motor load and use it to simulate a motor driver schematic and all its effects.... More specifically, you will Create an accurate motor model in MATLAB or Verilog A including BEMF (Back Electro Magnetic Force) effects...

22 Nov
Digital ASIC Design and DSP Internship
Location: Leuven, Flemish Brabant
Salary: N/A

. Bonus points if you know Verilog/VHDL! ***Keysight is an Equal Opportunity Employer.***...

21 Nov
SoC RTL Designer
Location: Pune, Maharashtra - Lint, Antwerp
Salary: N/A

, and both Verilog and System Verilog. The qualified candidate will be working in SoC integration and associated quality checks...

15 Nov
Internship - Healthcare IC Development
Location: Leuven, Flemish Brabant
Salary: N/A

Your Profile First or second year of Master of Science –Engineer school Affinity with VHDL/Verilog/SystemC/Python language...

09 Nov
Digital IC Design Engineer (Staff or Principal)
Location: Brussels
Salary: €110000 - 160000 per year

responsibilities. Expertise in embedded CPUs, and AMBA bus protocols (AHB/APB). Experience in RTL design, System Verilog Deep...