Found 4 jobs on 1 pages

12 Apr
DIGITAL IC VERIFICATION ENGINEER
Location: Brussels
Salary: N/A

and written English Thorough understanding of the VHDL/Verilog/SystemVerilog/UVM and Cadence tools Ability to create and execute...

07 Apr

of Verilog and SystemVerilog for design and verification - Experience with RTL lint - Knowledgeable about DFT and ATPG...

10 Feb
Senior Digital IC Verification Engineer
Location: Belgium
Salary: N/A

(Verilog, SystemVerilog, VHDL) - 7+ years of experience in digital verification with hands on experience with SystemVerilog..., Verilog and UVM. - Experience in SoC design flow – RTL design, simulation, verification, DFT, signoff (Cadence, Synopsys...

01 Feb
CONTRACT] ASIC Design & Verification Engineer
Location: Belgium
Salary: N/A

of Verilog and SystemVerilog for design and verification - Experience with RTL lint - Knowledgeable about DFT and ATPG...