Found 827 jobs on 83 pages

02 May
Senior Digital Integration & Timing Engineer
Location: Irvine, CA
Salary: N/A

) with functional ECOs in the mix. Familiarity with DFT and backend related methodologies and tools. Proficient with RTL Verilog/VHDL...

02 May
ASIC Design Engineer - Neural Engine DMA
Location: Cupertino, CA
Salary: N/A

SoC front-end ASIC RTL digital logic design using Verilog, or System Verilog. Experience working multi-functionally...

02 May
FPGA Engineer (Andover, MA)
Location: Andover, MA
Salary: N/A

in Hardware Descriptive Languages (Verilog or System Verilog preferred). 2+ years of experience with FPGA and CPLD...

02 May
Senior Staff IC Design Engineer
Location: Santa Clara, CA
Salary: $124160 - 186000 per year

with network IC. Good understanding of silicon debugging and validation of mixed-signal/digital ICs. Fluent in System Verilog...

02 May
ASIC Design Engineer - Neural Engine DMA
Location: Cupertino, CA
Salary: N/A

SoC front-end ASIC RTL digital logic design using Verilog or System Verilog. Experience working multi-functionally...

02 May
Sr DFT Engineer, Hardware Compute Group
Location: Sunnyvale, CA
Salary: $127300 per year

implementation. - Experience in writing verilog/system verilog RTL related to DFT logic design. - Experience in Chip level DFT...

02 May
Senior Digital Integration & Timing Engineer
Location: Sunnyvale, CA
Salary: N/A

) with functional ECOs in the mix. Familiarity with DFT and backend related methodologies and tools. Proficient with RTL Verilog/VHDL...

02 May
Principal Design Verification Engineer - PCIe
Location: Austin, TX
Salary: N/A

. AMBA5 CHI, AMBA4 ACE or AXI). Previous experience in specification, creation, and debug of System Verilog/UVM constrained...

02 May

. Familiarity or experience with RTL coding using Verilog, SystemVerilog, or similar language. Excellent critical thinking skills...

02 May
SoC Physical Design Engineer, PnR
Location: Sunnyvale, CA
Salary: N/A

functional teams across a variety of fields. Experience with Verilog, VHDL, Python, Perl, TCL and/or SPICE is beneficial...