Found 814 jobs on 82 pages

02 May
Digital Integration & Timing Engineer
Location: San Diego, CA
Salary: N/A

) with functional ECOs in the mix. Familiarity with DFT and backend related methodologies and tools. Proficient with RTL Verilog/VHDL...

02 May
Analog Design, Staff Engineer
Location: Boston, MA - Boxborough, MA
Salary: $105000 - 157000 per year

simulators and simulation methods. Knowledgeable in Verilog-A for analog behavioral modeling and simulation-control/data-capture...

02 May
Principal Design Verification Engineer
Location: Mountain View, CA
Salary: $133600 per year

involving Ethernet interface. In depth knowledge of verification and debug principles, test benches, System Verilog, Universal...) Advanced eXtensible Interface (AXI) and Ethernet protocols. Substantial background in debugging RTL (Verilog) designs...

02 May
DSP FPGA Engineer
Location: Rockville, MD
Salary: N/A

. Strong written and communication skills. Hardware Description Languages: VHDL, Verilog Development Tools: Xilinx Vivado, Xilinx...

02 May
SoC DFT Engineer
Location: Cupertino, CA
Salary: N/A

for designs. Knowledge of Verilog and/or VHDL, and experience with simulators and waveform debugging tools. Knowledge...

02 May
Digital Integration & Timing Engineer
Location: San Diego, CA
Salary: $52.99 - 79.76 per hour

. Familiarity with DFT and backend related methodologies and tools. Proficient with RTL Verilog/VHDL. Knowledge of digital top...

02 May
Principal Logic Design Engineer
Location: Raleigh, NC
Salary: $133600 per year

Verilog/System Verilog, design verification collaboration, and CDC/Lint closure. 7+ years of experience in synthesis, timing...

02 May
Entry Level Professional - Digital Design Engineer (Summer 2024 Start)
Location: Westborough, MA
Salary: $93800 - 138750 per year

requirements, and that form the basis for clear and concise verification test plans. You will code designs in Verilog to meet...’s Degree and/or PhD in those fields. - Your coursework must have included some analog classes, Verilog or VHDL, basic...

02 May
Infinity Fabric Micro-Architect & RTL Design Engineer
Location: Santa Clara, CA
Salary: N/A

and timing requirements. Write easily readable and synthesizable Verilog RTL Run some unit level testing to deliver quality...-processor coherency, memory ordering, i/o ordering, interrupts, MMU and caches Excellent knowledge of Verilog and System...

02 May
Senior Digital Integration & Timing Engineer
Location: Sunnyvale, CA
Salary: N/A

) with functional ECOs in the mix. Familiarity with DFT and backend related methodologies and tools. Proficient with RTL Verilog/VHDL...