Found 910 jobs on 91 pages

02 Nov
Emulation Verification Engineer
Location: Sunnyvale, CA
Salary: N/A

activities using Verilog/System Verilog/UVM. Minimum Qualifications Minimum Qualifications BS and 10+ years of relevant.... Experience with System Verilog verification environments including C/C++ DPI, UVM. Key Qualifications Key Qualifications...

02 Nov
High Speed Analog/Mixed-Signal IC Design Engineer
Location: San Diego, CA
Salary: N/A

/debugging RTL, developing System Verilog models, and performing behavioral simulations to explore new architectural performance...

02 Nov
High Speed Analog/Mixed-Signal IC Design Engineer
Location: San Diego, CA
Salary: N/A

/debugging RTL, developing System Verilog models, and performing behavioral simulations to explore new architectural performance...

02 Nov
Graphics FE Implementation Engineer
Location: Austin, TX
Salary: N/A

Qualifications Familiarity with Verilog and System Verilog Exposure to industry standard rtl2gds tools for synthesis, place...

02 Nov
Senior Design Verification Engineer
Location: Dallas, TX
Salary: N/A

System Verilog, UVM Experience with complex RAL configurations Experience with full verification flow including coverage...

02 Nov
High Speed Analog/Mixed-Signal IC Design Engineer
Location: Austin, TX
Salary: N/A

/debugging RTL, developing System Verilog models, and performing behavioral simulations to explore new architectural performance...

02 Nov
CPU Principal RTL Design Engineer
Location: Fort Collins, CO
Salary: N/A

across disciplines Prior experience with Digital RTL Design, Verilog HDL, and Scripting ACADEMIC CREDENTIALS: BS/MS in EE, CS, CSE...

02 Nov
Semiconductor IC Custom Circuit Design Engineers
Location: Chandler, AZ
Salary: N/A

, and optimization of memory circuits Perform circuit simulations using standard industry tools such as SPICE and VERILOG Able...

02 Nov

with multiple successful tape outs Deep knowledge about System Verilog, UVM and verification coverage matrix Strong experience...

02 Nov
Senior Formal Verification Engineer
Location: San Jose, CA
Salary: N/A

Verilog and UVM methodology expertise Must have 5+ years of experience and BSEE, MSEE preferred #FormalVerification #UVM...