Found 827 jobs on 83 pages

02 May
SoC DFT Engineer
Location: Cupertino, CA
Salary: N/A

for designs. Knowledge of Verilog and/or VHDL, and experience with simulators and waveform debugging tools. Knowledge...

02 May
DSP FPGA Engineer
Location: Rockville, MD
Salary: N/A

. Strong written and communication skills. Hardware Description Languages: VHDL, Verilog Development Tools: Xilinx Vivado, Xilinx...

02 May
Standard Cell Design Methodology & Flow Engineer
Location: Santa Clara, CA
Salary: N/A

of Verilog/SystemVerilog, UDPs, Verilog simulation and formal verification Exposure to Design For Test, scan concept and write... sophisticated digital block in Verilog/SystemVerilog, run simulations or formal check for verification. - Use data analysis...

02 May
Engineer: FPGA/RTL Design - III
Location: Hillsboro, OR
Salary: N/A

creation and functional verification. Effective behavioral modeling and testing of circuits in Verilog and System Verilog..., as well as logical equivalence verification between Schematic and Verilog models. UPF (Unified Power Format) creation using low power...

02 May
Principal Design Verification Engineer
Location: Mountain View, CA
Salary: $133600 per year

involving Ethernet interface. In depth knowledge of verification and debug principles, test benches, System Verilog, Universal...) Advanced eXtensible Interface (AXI) and Ethernet protocols. Substantial background in debugging RTL (Verilog) designs...

02 May
Senior Digital Integration & Timing Engineer
Location: San Diego, CA
Salary: N/A

) with functional ECOs in the mix. Familiarity with DFT and backend related methodologies and tools. Proficient with RTL Verilog/VHDL...

02 May
Principal Digital Design Engineer - Technical Lead
Location: San Jose, CA
Salary: N/A

, Amba, Protocol Bus Architecture, DFT, ARM/RISC, AXI/AHB/APB, Multi-core CPU, VHDL/Verilog and Fault Coverage Analysis... - Some wireless experience - i.e. WiFi, iOT, Bluetooth, 4G, 5G, etc. - Verilog, VHDL & System Verilog language experience & tools...

02 May
Digital Integration & Timing Engineer
Location: Irvine, CA
Salary: N/A

) with functional ECOs in the mix. Familiarity with DFT and backend related methodologies and tools. Proficient with RTL Verilog/VHDL...

02 May
Senior Staff Design Verification Engineer
Location: Austin, TX
Salary: $139100 - 205790 per year

constrained-random verification test environment using Verilog/System Verilog, UVM and C programming, including testbenches... of behavioral coding in verilog and SystemVerilog Experience programming in C or C++ and in scripting using Python, PERL or Bash...

02 May
Principal Logic Design Engineer
Location: Raleigh, NC
Salary: $133600 per year

Verilog/System Verilog, design verification collaboration, and CDC/Lint closure. 7+ years of experience in synthesis, timing...