Found 910 jobs on 91 pages

23 Oct
HPC Processor Digital Architect
Location: Linthicum, MD
Salary: N/A

with a Bachelor's 3 years with a Masters and 0 years with a PhD). Must be familiar with VHDL, Verilog, or SystemVerilog... years of relevant experience (6 years with a Masters or 3 years with a PhD). Must be familiar with VHDL, Verilog...

23 Oct
Graphics (GPU) Architectural Modeling Engineer
Location: Orlando, FL
Salary: N/A

. Experience with performance analysis and debug. Experience with HDLs, Verilog, System Verilog or VHDL. Experience with turning...

23 Oct
R&D IC Design Engineer
Location: Irvine, CA
Salary: N/A

process including Verilog, VHDL, Unix/Perl Scripting or Python, and C. Self-motivated, excellent communication skills...

23 Oct
Analog Design Engineer - TPG
Location: Dallas, TX
Salary: N/A

industry simulators such as FINESIM, HSPICE and VERILOG. Responsible for reliability verification Assist in design validation...

23 Oct
Graphics (GPU) Architectural Modeling Engineer
Location: Austin, TX
Salary: N/A

and debug. Experience with HDLs, Verilog, System Verilog or VHDL. Education & Experience Education & Experience...

23 Oct
Silicon Verification Engineer 3
Location: Mountain View, CA
Salary: $52 - 63 per hour

years' experience with UVM Must Have 3 years' experience with System Verilog Must Have 3 years' experience with Test Bench..., Computer Science, or related degree required 3+ years of relevant experience required. Proficient in using Verilog and VMM...

23 Oct
Analog IC Design Engineer
Location: Cedar Rapids, IA
Salary: $76100 - 138900 per year

that resulted in high-volume manufacturing Layout floor planning and design experience Verilog-A modeling Preferred...

22 Oct
Design for Test Engineer
Location: California
Salary: N/A

Preferred skills SerDes IP , RTL, Verilog...

22 Oct
Senior Clocks Methodology Engineer
Location: Santa Clara, CA
Salary: N/A

. Strong interpersonal and collaboration skills are required. Ways to stand out from the crowd: Prior experience in RTL design (Verilog...

22 Oct
Senior ASIC Design Engineer
Location: Santa Clara, CA
Salary: N/A

and design the SOC clocks to satisfy all the architectural constraints. Your understanding of System Verilog will be valuable... environment. Experience in RTL design (Verilog), verification and logic synthesis. Strong coding skills in Perl...