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or above in Electronic Engineering or equivalent; 5 Years or above of solid experience in one or more of the following areas: Verilog-based... logic design and synthesis, constrained random testbench with System Verilog & UVM, assertion based design verification... Apply Now

Experience in one or more of the following areas is advantage: Verilog based logic design and synthesis, constrained random... testbench with System Verilog & UVM, assertion-based design verification Knowledge of low power logic design Knowledge... Apply Now

: Verilog/VHDL, System Verilog, Python, C/C++, Matlab; R&D experiences of using Cadence and Synopsys EDA tools or machine... Apply Now