Found 715 jobs on 72 pages

09 Jun
Senior ASIC Verification Engineer
Location: Petaluma, CA
Salary: N/A

Electrical Engineering coupled with proven experience in ASIC development with Verilog. Experience with ASIC design..., including proficiency in UVM and System Verilog. Experience with modern SoC design architectures, ARM/MiPs type processor...

09 Jun
Hardware Engineering Internships
Location: Sunnyvale, CA
Salary: N/A

, PH, Obj-C, VHDL, Verilog RTL, Digital Logic Design Experience using measurement equipment, such as spectrum analyzers...

09 Jun
Senior ASIC Verification Engineer
Location: Petaluma, CA
Salary: N/A

Electrical Engineering coupled with proven experience in ASIC development with Verilog. Experience with ASIC design..., including proficiency in UVM and System Verilog. Experience with modern SoC design architectures, ARM/MiPs type processor...

09 Jun
Senior Principal Digital IC Design Engineer
Location: Irvine, CA
Salary: $162000 - 239760 per year

System Verilog RTL coding techniques. Experience in high speed, multiple clock domain designs Expertise in PCIe, CXL...

09 Jun
CPU Physical Design Engineer - Austin, TX
Location: Austin, TX
Salary: N/A

sizing. Perform feasibilities to validate implementability, area, timing and power. Synthesize the Verilog RTL into gate...

09 Jun
Senior ASIC Design Verification Engineer
Location: San Jose, CA
Salary: N/A

Ambitious and dedicated Good interpersonal skills Solid knowledge and strong experience of System Verilog, UVM, and C/C..., System Verilog Strong knowledge on basic concepts of VLSI, SoC architecture Ethernet and packet processing experience H1...

09 Jun
Memory Controller Micro-Architect/Logic Designer
Location: Austin, TX
Salary: N/A

RTL design on high performance digital designs Verilog expertise is required as is an understanding of ASIC design flow...

09 Jun
Senior FPGA Engineer
Location: Pleasanton, CA
Salary: $125000 - 175000 per year

: HDL coding (Verilog and/or VHDL) for synthesizable RTL and verification EDA tools Vivado and/or Quartus for FPGA design...

09 Jun
FPGA Engineer
Location: Pleasanton, CA
Salary: N/A

, both written and verbal. Required expertise: RTL coding experience in either VHDL, Verilog and/or SystemVerilog. Develop end...

08 Jun
ASIC Design Engineer (Security Group)
Location: San Diego, CA
Salary: $108000 - 162000 per year

of ASIC design flow: Architecture, Microarchitecture, verilog/system-verilog RTL design, Clock Domain Crossings, DFT...