Found 903 jobs on 91 pages

05 Oct
CAD Engineer, Logic Equivalence & ECO
Location: Beaverton, OR
Salary: N/A

or Perl scripting languages. Knowledge of Verilog or SystemVerilog coding for hardware design or verification...

05 Oct
CAD Engineer, Logic Equivalence & ECO
Location: Austin, TX
Salary: N/A

or Perl scripting languages. Knowledge of Verilog or SystemVerilog coding for hardware design or verification...

04 Oct
CAD Engineer - Formal Verification
Location: Cupertino, CA
Salary: N/A

Experience scripting in Python, Perl, Kotlin or TCL Experience in Software Development with Test in-mind Knowledge in Verilog... and System Verilog Minimum requirement of BS and 3+ years of relevant industry experience Key Qualifications Key...

04 Oct
CAD Engineer - Formal Verification
Location: Cupertino, CA
Salary: N/A

scripting in Python, Perl, Kotlin or TCL Experience in Software Development with Test in-mind Experience in Verilog and System... Verilog Minimum requirement of BS and 10+ years of relevant industry experience Key Qualifications Key Qualifications...

04 Oct
Principal Design Engineer - TPG
Location: Boise, ID
Salary: N/A

and VERILOG Drive the design and development of schematic blocks such as memory array, control logic, address decode, datapath...

04 Oct
Analog IC Design Engineer
Location: Cupertino, CA
Salary: N/A

in presence of device mismatch Experience in C / Matlab / Verilog modeling Strong device physics knowledge as it applies...

04 Oct
Analog IC Design Engineer
Location: Cupertino, CA
Salary: N/A

in presence of device mismatch Experience in C / Matlab / Verilog modeling Strong device physics knowledge as it applies...

04 Oct
RTL Design Engineer
Location: Cupertino, CA
Salary: $121900 - 183600 per year

, Verilog and SystemVerilog Deep knowledge of front-end tools (Verilog simulators, linters, clock-domain crossing checkers...

04 Oct
Emulation Engineer
Location: Beaverton, OR
Salary: N/A

with C/C++, DPI and System Verilog, Verilog, VHDL design. Experience with waveform debug tools, Verdi/SimVision Knowledge...

04 Oct
ASIC Engineering Technical Leader
Location: San Jose, CA
Salary: N/A

Prior experience in Asic verification using UVM/System Verilog. Prior experience building test benches from scratch, hands... on experience with System Verilog constraints, structures and classes. prior experience with Perl and/or Python scripting Prior...