Found 903 jobs on 91 pages

09 Oct
CPU Microarchitect/RTL Engineer - Execution, Load/Store
Location: Santa Clara, CA
Salary: N/A

industry experience Knowledge of microprocessor architecture Knowledge of Verilog and/or VHDL Experience with simulators...

09 Oct
CPU Power Management Microarchitect/RTL Engineer
Location: Santa Clara, CA
Salary: N/A

Minimum BS and 10+ years of relevant industry experience Knowledge of microprocessor architecture Knowledge of Verilog...

09 Oct
Positioning, Navigation and Timing Engineer
Location: Dayton, OH
Salary: $81250 - 146875 per year

Description Language (VHDL), and Verilog experience. Original Posting Date: 2024-10-07 While subject to change based on business needs...

09 Oct
CPU ML Microarchitect/RTL Engineer
Location: Santa Clara, CA
Salary: N/A

of microprocessor architecture Knowledge of Verilog and/or VHDL Experience with simulators and waveform debugging tools Knowledge...

09 Oct

architecture Knowledge of Verilog and/or VHDL Experience with simulators and waveform debugging tools Knowledge of logic design...

09 Oct
CPU CDC/STA Engineer
Location: Santa Clara, CA
Salary: N/A

• Working with RTL and DV teams to recommend System Verilog assertions needed to support CDC/RDC/STA constraints and assumptions... (RDC) solutions Experience in Verilog Key Qualifications Key Qualifications Preferred Qualifications Preferred...

09 Oct
CPU Cache Microarchitect/RTL Engineer
Location: Santa Clara, CA
Salary: N/A

of microprocessor architecture Knowledge of Verilog and/or VHDL Experience with simulators and waveform debugging tools Knowledge...

09 Oct
CPU Microarchitect/RTL Engineer - Fetch, Out of Order
Location: Santa Clara, CA
Salary: N/A

architecture Knowledge of Verilog and/or VHDL Experience with simulators and waveform debugging tools Knowledge of logic design...

09 Oct
CPU Microarchitect/RTL Engineer - Execution, Load/Store
Location: Santa Clara, CA
Salary: N/A

industry experience Knowledge of microprocessor architecture Knowledge of Verilog and/or VHDL Experience with simulators...

09 Oct
CPU CDC/STA Engineer
Location: Santa Clara, CA
Salary: $121900 - 183600 per year

• Working with RTL and DV teams to recommend System Verilog assertions needed to support CDC/RDC/STA constraints and assumptions... Preferred Qualifications Preferred Qualifications Experience in Verilog, SystemVerilog Assertions (SVA), and Design...