Found 4 jobs on 1 pages

21 Dec
Analog Centric Mixed Signal Verification Engineer (f/m/div)
Location: Villach, Kärnten
Salary: N/A

and digital design experience as well as know-how SPICE, VHDL, (System)Verilog Solid programming skills (e.g. Perl, C, C...

04 Dec
Cellular IP Design Engineer (m/f/d)
Location: Linz
Salary: €64734 per year

modeling skills for synthesis and simulation using modern modeling language. (Verilog / System Verilog). Hands-on experience... design and quality checks such as Lint and CDC/RDC. Proficient in using (System)Verilog, the ability to analyze RTL/Netlist...

27 Nov
Experienced AMS Design Verification Engineer (m/f/d)
Location: Linz
Salary: €79204 per year

. Minimum Qualifications Minimum Qualifications Knowledge of System Verilog test-bench language and UVM (Universal Verification Methodology... Familiarity with system design using C++, Python or Verilog Familiarity with FPGA emulation platforms The minimum salary...

23 Nov
Internship: Digital Hardware Design Engineer (f/m/d)
Location: Gratkorn, Steiermark
Salary: N/A

of Linux OS and/or bash/tcsh scripting Basic knowledge of Verilog or VHDL Basic knowledge of Centralized Version Control...