Found 793 jobs on 80 pages

17 May
Sr. Memory Controller Micro-Architect/Logic Designer
Location: Austin, TX
Salary: N/A

of successful Architectural through RTL design on high performance digital designs Verilog expertise is required as is a deep understanding...

16 May
FPGA DSP Firmware Design Engineer
Location: El Cajon, CA
Salary: $81250 - 146875 per year

descriptor languages, HDL (VHDL, Verilog), based on customer requirements and/or MATLAB model(s). Collaborate with a multi..., design, and implement HDL test benches in hardware description languages, HDL (VHDL, Verilog), for code validation...

16 May
FPGA DSP Firmware Design Engineer
Location: National City, CA
Salary: $81250 - 146875 per year

descriptor languages, HDL (VHDL, Verilog), based on customer requirements and/or MATLAB model(s). Collaborate with a multi..., design, and implement HDL test benches in hardware description languages, HDL (VHDL, Verilog), for code validation...

16 May
FPGA DSP Firmware Design Engineer
Location: San Diego, CA
Salary: $81250 - 146875 per year

descriptor languages, HDL (VHDL, Verilog), based on customer requirements and/or MATLAB model(s). Collaborate with a multi..., design, and implement HDL test benches in hardware description languages, HDL (VHDL, Verilog), for code validation...

16 May
FPGA DSP Firmware Design Engineer
Location: Cardiff By The Sea, CA
Salary: $81250 - 146875 per year

descriptor languages, HDL (VHDL, Verilog), based on customer requirements and/or MATLAB model(s). Collaborate with a multi..., design, and implement HDL test benches in hardware description languages, HDL (VHDL, Verilog), for code validation...

16 May
FPGA DSP Firmware Design Engineer
Location: Chula Vista, CA
Salary: $81250 - 146875 per year

descriptor languages, HDL (VHDL, Verilog), based on customer requirements and/or MATLAB model(s). Collaborate with a multi..., design, and implement HDL test benches in hardware description languages, HDL (VHDL, Verilog), for code validation...

16 May
FPGA DSP Firmware Design Engineer
Location: Rancho Santa Fe, CA
Salary: $81250 - 146875 per year

descriptor languages, HDL (VHDL, Verilog), based on customer requirements and/or MATLAB model(s). Collaborate with a multi..., design, and implement HDL test benches in hardware description languages, HDL (VHDL, Verilog), for code validation...

16 May
FPGA DSP Firmware Design Engineer
Location: Arlington, VA
Salary: $81250 - 146875 per year

descriptor languages, HDL (VHDL, Verilog), based on customer requirements and/or MATLAB model(s). Collaborate with a multi..., design, and implement HDL test benches in hardware description languages, HDL (VHDL, Verilog), for code validation...

16 May
FPGA DSP Firmware Design Engineer
Location: La Jolla, CA
Salary: $81250 - 146875 per year

descriptor languages, HDL (VHDL, Verilog), based on customer requirements and/or MATLAB model(s). Collaborate with a multi..., design, and implement HDL test benches in hardware description languages, HDL (VHDL, Verilog), for code validation...

16 May
Sr. Electrical Engineer, Digital ASIC design
Location: Plantation, FL
Salary: N/A

level digital implementation. In this position you will do the following: - Verilog RTL-level digital designs, debug... experience Strong written and verbal communication skills Strong RTL coding and documentation practices Verilog (preferred...

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