Found 767 jobs on 77 pages

18 May
Senior Microelectronics Design Engineer
Location: Rancho Santa Fe, CA
Salary: N/A

, structural, reliability) Hardware Programming: FPGA (i.e. Verilog, VHDL), Programming (Linux command line/scripting, Python...

18 May
Senior Microelectronics Design Engineer
Location: La Jolla, CA
Salary: N/A

, structural, reliability) Hardware Programming: FPGA (i.e. Verilog, VHDL), Programming (Linux command line/scripting, Python...

18 May
Senior Microelectronics Design Engineer
Location: Chula Vista, CA
Salary: N/A

, structural, reliability) Hardware Programming: FPGA (i.e. Verilog, VHDL), Programming (Linux command line/scripting, Python...

18 May
Senior Microelectronics Design Engineer
Location: El Cajon, CA
Salary: N/A

, structural, reliability) Hardware Programming: FPGA (i.e. Verilog, VHDL), Programming (Linux command line/scripting, Python...

18 May
Senior Microelectronics Design Engineer
Location: Cardiff By The Sea, CA
Salary: N/A

, structural, reliability) Hardware Programming: FPGA (i.e. Verilog, VHDL), Programming (Linux command line/scripting, Python...

18 May
Eng Sr Prin - Elec
Location: Totowa, NJ
Salary: N/A

experience in FPGA (preferred) or ASIC Design / Development VHDL (preferred) or Verilog HDL coding Familiarity with Xilinx...

18 May
ASIC Architect
Location: San Jose, CA
Salary: N/A

How to Qualify Bachelor’s degree in engineering 5+ years of ASIC experience RTL design experience in Verilog/SystemVerilog...

18 May
ASIC Digital Design, Staff Engineer
Location: Mountain View, CA - Sunnyvale, CA
Salary: $122000 - 188000 per year

performance and low power Must have strong digital design fundamentals Hands-on expertise with Verilog, System Verilog Hands...

18 May

System Verilog. Exposure to design and verification tools (VCS or equivalent simulation tools, debug tools like Debussy...

18 May
IPU/AI Logic Design Lead
Location: San Jose, CA
Salary: N/A

design PREFERRED EXPERIENCES: 15+ years of Strong design expertise in ASIC designs, RTL design in Verilog/System Verilog...