Found 910 jobs on 91 pages

16 Oct
Wireless RTL Design Engineer
Location: Sunnyvale, CA
Salary: $121900 - 183600 per year

design techniques. Excellent communication skills and self-motivation. Familiar with Verilog/Vhdl and MATLAB/C programming...

16 Oct
Software Defined Radio (SDR) Engineer with Secret
Location: Aberdeen Proving Ground, MD
Salary: N/A

tools (e.g., JIRA) is required. - Experience with VHDL, Verilog, or MATLAB System Generator with competency in learning...

16 Oct
Embedded Hardware Systems Engineer
Location: Boulder, CO
Salary: $80000 - 150000 per year

design using Verilog and/or VHDL Experience with printed circuit board layout and assembly Proficiency in Python...

16 Oct
Senior FPGA Engineer
Location: Wilton, CT
Salary: N/A

knowledge of signal algorithms Knowledge/hands-on experience with software/technical tools VHDL, System Verilog, UVM...

16 Oct
Embedded Hardware Systems Engineer
Location: Boulder, CO
Salary: $80000 - 150000 per year

design using Verilog and/or VHDL Experience with printed circuit board layout and assembly Proficiency in Python...

16 Oct
Sr. Silicon Design Verification Engineer
Location: San Jose, CA
Salary: N/A

controllers, especially DDR4/5, LPDDR4/5, and HBM2/2E/3. Requires experience with development of UVM/OVM and/or Verilog, System... Verilog test benches and usage of simulation tools/debug environments such as Synopsys VCS, Cadence IES to verify Full-Chip...

16 Oct
Embedded Hardware Systems Engineer
Location: Boulder, CO
Salary: $80000 - 150000 per year

design using Verilog and/or VHDL Experience with printed circuit board layout and assembly Proficiency in Python...

15 Oct
Graphics (GPU) Architectural Modeling Engineer
Location: Santa Clara, CA
Salary: N/A

Pipeline. Experience with performance analysis and debug. Experience with HDLs, Verilog, System Verilog or VHDL. Experience...

15 Oct
Graphics (GPU) Architectural Modeling Engineer
Location: Santa Clara, CA
Salary: N/A

and debug. Experience with HDLs, Verilog, System Verilog or VHDL Education & Experience Education & Experience...

15 Oct
Staff Digital Design Engineer
Location: Austin, TX
Salary: $112500 - 215900 per year

, design, analysis, and HDL (Verilog/System Verilog) coding Detailed documentation, test vector development, lab test..., Python, SKILL), and version control systems (e.g. SVN, SOS) Working knowledge of System Verilog and/or UVM Experience...