Found 293 jobs on 30 pages

24 Oct
SMTS Silicon Design Engineer AECG ASIC DV Lead
Location: Bangalore, Karnataka
Salary: N/A

Verification experience with strong Verilog, System Verilog, C and UVM/OVM knowledge Candidate should be able to develop Testbench... with Verilog, System Verilog, C, and C++ Worked on any High Speed Interface like PCIE/DDR/USB/Other, Good understanding of AXI/AHB...

24 Oct

Verification experience with strong Verilog, System Verilog, C and UVM/OVM knowledge Candidate should be able to develop Testbench... in debugging firmware and RTL code using simulation tools Proficient in using UVM testbenches Experienced with Verilog, System...

24 Oct
Senior IC Design Engineer
Location: India
Salary: N/A

. Proficiency with Verilog NC, Verilog XL tools 7. Strong fundamentals in digital design and Coding/Verifying complex RTL...

24 Oct
Manager - Design Validation
Location: Hyderabad, Telangana
Salary: N/A

is essential. NAND product design development, validation, characterization & qualification preferred. Experience in verilog..., Magnum, etc) Knowledge in writing testbenches in SV, Verilog, Verilog-AMS, Spice Fundamental programming/scripting skills...

24 Oct
Technical Lead - Hardware
Location: Bangalore, Karnataka
Salary: N/A

, Wireless etc. - Programming Experience C/C++ would be nice to have. - Experience with HDL (VHDL/Verilog) would be nice...

23 Oct

of experience 6+ Required. Expertise in System Verilog, methodology based testbench architectures such as UVM, and System Verilog...

23 Oct
WIFI PHY - Design Verification - Staff Engineer
Location: Bangalore, Karnataka
Salary: N/A

: Strong System Verilog/UVM based verification skills & experience with assertion & coverage-based verification methodology...

20 Oct
Sr. Silicon Design Engineer
Location: Hyderabad, Telangana
Salary: N/A

is required. Proven experience in Silicon IP development process, methodologies, Design for Test methodologies Experience with Verilog...

19 Oct
Sr. Silicon Design Engineer
Location: Hyderabad, Telangana
Salary: N/A

of Verilog, System Verilog and VHDL Scripting language experience: Perl, tcl, Makefile, shell preferred ACADEMIC CREDENTIALS...

19 Oct
MTS Silicon Design Engineer
Location: Hyderabad, Telangana
Salary: N/A

firmware and RTL code using simulation tools Good working knowledge of Verilog, System Verilog and VHDL Scripting language...