Found 362 jobs on 37 pages

14 Sep
Power Core IP DV Sr Lead Engineer
Location: Bangalore, Karnataka
Salary: N/A

to implement and analyze system Verilog assertion and coverage(code, toggle, functional) . Work alongside other members of the... and PCIe Protocol is desirable. Good understanding of processor based Soc level verification which includes native ,Verilog...

14 Sep
DV Engineer (12+ years exp)
Location: Hyderabad, Telangana
Salary: N/A

: Strong knowledge in IP/SOC design methodologies. Sound knowledge of RTL/SOC design/integration with Verilog/system Verilog Mentoring... with Verilog, System Verilog, C, and C++ Graphics pipeline knowledge Developing UVM based verification frameworks and testbenches...

14 Sep
GPU Functional Verification Sr Engineer
Location: Bangalore, Karnataka
Salary: N/A

below, Strong knowledge of UVM based System Verilog TB Knowledge of GPU pipeline design is a plus, not mandatory Proficiency with formal tools...

14 Sep
DDR DV Staff Verification Engineer
Location: Bangalore, Karnataka
Salary: N/A

. Required skillset: Experience in verification and general computational logic design/verification concepts. Expertise in Verilog.../System Verilog and UVM/OVM. Strong debugging, Analytical and problem-solving skills. Experience in developing Monitors...

14 Sep
DDR / Memory Verification Engineer
Location: Bangalore, Karnataka
Salary: N/A

environments Experienced with Verilog, System Verilog, C, and C++ Graphics pipeline knowledge Developing UVM based verification...

13 Sep
Staff Design Engineer
Location: Hyderabad, Telangana
Salary: N/A

in Finesim and/or Hspice Experience with power network analysis. Extensive knowledge in verilog modeling and simulation...

13 Sep
Architect - GPU Performance Analysis
Location: Bangalore, Karnataka
Salary: N/A

on competence in programming (C/C++) and scripting (Perl/Python). Exposure to Verilog/System Verilog, SystemC/TLM...

13 Sep
DSP Technical program Manager
Location: Bangalore, Karnataka
Salary: N/A

, across multiple groups with basic knowledge on scripting and Verilog. Should have excellent inter-personal, communication skills...

13 Sep
CPU/IP Design Manager
Location: Bangalore, Karnataka
Salary: N/A

efficiency of the team PREFERRED EXPERIENCE: 10+years of experience in Digital IP/ASIC design and Verilog RTL development 3...

13 Sep
IBM SENIOR LOGIC DESIGN ENGINEER – Core Execution(VSU) Unit
Location: Bangalore, Karnataka
Salary: N/A

of RTL design with Verilog or VHDL Nice to haves Knowledge of instruction dispatch and load/store units Knowledge...