Found 94 jobs on 10 pages

03 Jul
ASIC Digital Design, Staff Engineer
Location: Kanata, ON - Markham, ON
Salary: N/A

/CDR. Experience with ADC-based transceivers is a plus. Knowledge of Verilog is a plus Must exhibit ability to produce...

01 Jul
ASIC Verification Engineer
Location: Ottawa, ON
Salary: N/A

Verilog PCIe (2+ years) Subsystem Level Verification (Transaction, data link) Verilog Vivado Quartus Shell scripting...

30 Jun
Fpga Design Engineer
Location: Ottawa, ON
Salary: N/A

and integrating at the block and subsystem level. Hard Skills 8+ Years of FPGA or ASIC RTL design RTL design in Verilog... and System Verilog FPGA design and CAD tools or ASIC front-end CAD tools Networking protocols such as Ethernet Scripting...

30 Jun
Principal SW/FW Engineer
Location: Kanata, ON
Salary: N/A

test flows, FPGA emulation, hardware languages such as Verilog Familiarity with lab equipment such as oscilloscopes...

30 Jun
Design Verification, Principal Engineer
Location: Richmond Hill, ON
Salary: N/A

or related fields with 5+ years of experience. Proficient in System Verilog and Object-oriented programming Well versed...

29 Jun
Silicon Design Engineer 2
Location: Markham, ON
Salary: N/A

and debug on platform during lab activities PREFERRED EXPERIENCE: Knowledge of Verilog and C/C++Knowledge of scripting...

26 Jun
Fpga Design Engineer
Location: Ottawa, ON
Salary: N/A

- 8+ Years of industry experience in FPGA or ASIC RTL design - Excellent RTL design skills in Verilog and System Verilog... - Working knowledge of networking protocols such as Ethernet Top Skills Details: rtl design, fpga design, verilog, system...

21 Jun
Analog Design, Principal Engineer
Location: Nepean, ON
Salary: N/A

Verilog-A for analog behavioral modeling and simulation-control/data-capture. Experience with TCL, Perl, C, Python, MATLAB...

19 Jun
Analog Mixed Signal Design Engineer
Location: Markham, ON
Salary: N/A

and components using Verilog/System Verilog Debugging in digital and mixed-signal simulation environment. Power-optimization...

15 Jun
Design Verification Engineer
Location: Vancouver, BC
Salary: N/A

System Verilog/UVM Analyzing Functional, Code, and Test Plan Coverage Implementing Assertions, Checkers, and Monitors...: Digital Design in RTL, Verilog HDL Testbench Architecture, System Verilog, OVM/UVM/VMM C/C++, Java, or other object-oriented...