Found 77 jobs on 8 pages

06 Oct

. Micro-architecture of ASIC blocks and sub-systems Design and implement complex RTL logic (mainly Verilog or System Verilog...

06 Oct
Staff ASIC Design Engineer – Constraints & RTL
Location: Ottawa, ON
Salary: N/A

Verilog or System Verilog), run block-level simulation, ASIC synthesis, timing closure. Interface with the verification team...

05 Oct
Memory System Verification Engineer
Location: Vancouver, BC
Salary: N/A

as needed. PREFERRED EXPERIENCE DESIRED: Experience in hardware/Firmware co-verification in UVM System Verilog, C-DPI, and gasket...

04 Oct
Design Verification Engineer
Location: Vancouver, BC
Salary: N/A

/Firmware co-verification in UVM System Verilog, C-DPI, and gasket structured testbench. Knowledge and development...

04 Oct
ASIC Design Lead / Architect – Display Interfaces
Location: Ottawa, ON
Salary: N/A

Verilog or System Verilog), run block-level simulation, ASIC synthesis, DFT insertion, timing closure. Interface with the...

27 Sep
Senior Hardware Designer
Location: Ottawa, ON
Salary: N/A

with ESD, EMI, and RF design considerations Ability to use Verilog, RTL, or HLS an asset What You’ll Be Doing: Develop the...

25 Sep
RTL Designer
Location: Canada
Salary: N/A

RTL modules written in Verilog/SystemVerilog Simulate and perform hardware-based testing, debug, and verification... and debug Strong knowledge with RTL programming languages Verilog/SystemVerilog (preferred), or VHDL Ability to read and write...