Found 13 jobs on 2 pages

02 May

benches and system verilog SOC level verification experience Fluent English EU passport / eligible to work in Portugal...

01 May
Intern (Technical-Engineering)
Location: Porto
Salary: N/A

: Technical skills: Evaluates and exercises various aspects of the development flow. May include such items as Verilog, System...-Verilog development, VMM, UVM, scripting, functional simulation, constraint development and functional verification...

01 May
Intern (Technical-Engineering)
Location: Porto
Salary: N/A

-Alone-Testbench (SATB). SATB verification environment has at its heart a System Verilog VMM component that uses the Synopsys AMBA VIP... the existing VMM/System Verilog testbench environment to UVM creating UVM elements is a key task that will enable...

01 May
Intern (Technical-Engineering)
Location: Porto
Salary: N/A

as Verilog/System-Verilog development, scripting, functional simulation, functional verification. Participate in evaluation..., Tcl, System-Verilog or verification methodologies VMM or UVM. Exposure to Unix scripting. Work on state-of-the-art...

13 Apr
ASIC Digital Design, Sr Engineer
Location: Lisbon
Salary: N/A

understanding of analog design Experience in Verilog/VHDL Proficiency in at least on programming language such as Python, C, C...++ and MATLAB Experience in System Verilog /VMM/UVM Exposure to Unix, Perl and TCL scripting At Synopsys, we're at the heart...

10 Apr
Hardware Engineering, Sr Engineer
Location: Porto
Salary: N/A

integrated circuitry using VHDL and/or (System) Verilog Knowledge in software programming languages like Tcl, C, C...

30 Mar
Project Engineering Management, Sr Staff Engineer
Location: Porto - Lisbon
Salary: N/A

qualifications Understanding of IC design flows Relevant work in previous projects Exposure to Verilog/VHDL Exposure to System... Verilog/UVM Exposure to Unix, Python and TCL scripting Knowledge of DisplayPort, HDMI or similar Business Area...

30 Mar
ASIC Digital Design, Sr Engineer
Location: Porto
Salary: N/A

Verilog. Participate in the behavioral modeling activities using Verilog/SystemVerilog language. Continuous documentation...

29 Mar
ASIC Digital Design, Sr Engineer
Location: Porto
Salary: N/A

and/or chip planning and architecture studies Participate in the implementation of mixed-signal blocks using Verilog Participate... in the behavioral modeling activities using Verilog/SystemVerilog language Continuous documentation and improvement...

24 Mar
Test & Validation Engineering, Sr Engineer
Location: Porto
Salary: N/A

and s-parameters. Verilog, Python and Matlab. UNIX operating systems and scripting. Laboratory bench instruments. Soft Skills...