Found 829 jobs on 83 pages

17 May
Electrical Engineer (Robotics)
Location: Boulder, CO
Salary: N/A

STEM Familiarity with: DSP and Microcontroller firmware development in C FPGA Design (Verilog and VHDL) System...

17 May

of successful Architectural through RTL design on high performance digital designs Verilog expertise is required as is a deep understanding...

17 May
Senior Static Timing Analysis (STA) Engineer
Location: San Jose, CA
Salary: N/A

Knowledge of basic Architecture and Verilog to collaborate with RTL and IP design teams for timing fixes Contribute to timing...

17 May
FPGA Design Verification Engineer
Location: Mountain View, CA
Salary: N/A

/Python/C/C++ Responsibilities: Architect and Create verification environments using System-Verilog and Universal... of experience in pre-silicon design verification Proficiency in C-shell scripting, Verilog-HDL & System Verilog. Strong knowledge...

17 May
Staff/Principal Hardware Applications Engineer
Location: Campbell, CA
Salary: N/A

with GPUs is strongly desired. Understanding and Experience of VHDL/Verilog debug Understanding of system-level considerations...

17 May
RTL Design Engineer
Location: San Jose, CA
Salary: N/A

-to-Chip interconnect PHY Designs. Design of digital circuits and components using Verilog/System Verilog Debugging in...

17 May
Digital Engineer 3
Location: Linthicum, MD
Salary: N/A

Design and/or ASIC Design Knowledge of System Verilog, Verilog and/or VHDL U.S. citizenship is required for all positions...

17 May
Principal FPGA Design Engineer
Location: Atlanta, GA
Salary: N/A

Circuits/Field Programmable Gate Arrays (ASICs / FPGAs) using C/C++ ior System Verilog. Experience with building and setting..., Verilog, VHDL, and proficient in Perl, C, Python & System Verilog (incl. OVM/UVM/SVA) Deep knowledge of physical...

17 May
EDA/CAD SW Engineer
Location: San Diego, CA
Salary: N/A

in the areas of RTL Synthesis (System Verilog - Netlist), Clock Tree Optimization, Clock gate conversion * Exposure...

17 May
Senior Power Electronics Engineer
Location: Minneapolis, MN
Salary: N/A

programs in Python and/or C. Verilog FPGA logic design and digital simulation experience. Cadence Allegro. Master’s degree...