Found 2 jobs on 1 pages

23 May
5G/6G FPGA Design - Asso. Principal Engineer / Lead Engineer / Senior Engineer
Location: Sha Tin District, Hong Kong
Salary: N/A

with Verilog RTL coding and testbench design Familiar with large FPGA development on Xilinx devices Experience with Xilinx...’s build flow including design entry in Verilog, synthesis, place and route, timing constraints and timing closure Experience...

20 May
Senior / IC Design Engineer - Digital Design
Location: Hong Kong
Salary: N/A

Electronic Engineering or equivalent; 5 Years or above of solid experience in one or more of the following areas: Verilog-based... logic design and synthesis, constrained random testbench with System Verilog & UVM, assertion based design verification...

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