Found 88 jobs on 9 pages

12 Apr
Ingénieur conception FPGA - Domaine de l'audiovisuel
Location: Antony, Hauts-de-Seine
Salary: €45000 - 65000 per year

PoC et analyses nécessaires sur les futurs produits à développer. Environnement technologique : FPGA, VHDL, Verilog...

10 Apr
Architecte FPGA F/H
Location: Val-d'Oise
Salary: N/A

de ressources, conception, vérification, gestion de configuration - maitrise des langages de description HDL (Verilog...

10 Apr
Architecte FPGA F/H
Location: Val-d'Oise
Salary: N/A

de ressources, conception, vérification, gestion de configuration - maitrise des langages de description HDL (Verilog...

10 Apr
Architecte FPGA F/H
Location: Val-d'Oise
Salary: N/A

de ressources, conception, vérification, gestion de configuration - maitrise des langages de description HDL (Verilog...

06 Apr

Knowledge required in Electronics, Mixed-signal Simulation, Python, Verilog, Verilog-AMS. A good level of English...

06 Apr
Team Leader Back-End (W/M)
Location: Paris
Salary: N/A

or an equivalent qualification. Proficient in designing digital functions using hardware description languages (Verilog/System-Verilog....rheso.tech/ Key words: Back-end, Design, People Management, Project Management, Cadence, Synopsys, Verilog, System-Verilog...

06 Apr
Team Leader Back-End (W/M)
Location: Grenoble, Isère
Salary: N/A

or an equivalent qualification. Proficient in designing digital functions using hardware description languages (Verilog/System-Verilog....rheso.tech/ Key words: Back-end, Design, People Management, Project Management, Cadence, Synopsys, Verilog, System-Verilog...

06 Apr
Team Leader Back-End (W/M)
Location: Caen, Calvados
Salary: N/A

or an equivalent qualification. Proficient in designing digital functions using hardware description languages (Verilog/System-Verilog....rheso.tech/ Key words: Back-end, Design, People Management, Project Management, Cadence, Synopsys, Verilog, System-Verilog...

06 Apr
Application Engineer - Associate Graduate Program (Verification) h/f
Location: Châtillon, Hauts-de-Seine
Salary: N/A

UVM, la simulation HDL VHDL et/ou Verilog, System Verilog et les techniques de vérification basées sur les assertions... spécifiques suivants : UNIX, Linux, Sun Solaris Langages - Verilog (comportemental, RTL, niveau porte), VHDL (comportemental, RTL...

06 Apr
Research Engineer in component Security H/F
Location: Isère
Salary: N/A

description languages: VHDL, Verilog and/or SystemVerilog An ability to lead a project independently Desired experience and/or skills...