Found 93 jobs on 10 pages

30 Sep
IC Design Verification Engineer, Intern
Location: Kanata, ON
Salary: N/A

design verification including test environment implementation and test plan development Knowledge of C, System Verilog...

30 Sep

cases/models and Verilog/system Verilog coding Build test platforms and perform system level testing Production validation... and scripts such as C++ /Python /C /Perl /Shell / UVM Verilog and System Verilog Good understanding of the digital systems...

29 Sep

Support debugging, improving simulation test cases/models and Verilog/system Verilog coding Build test platforms and perform... you to apply – Programming languages and scripts such as C++ /Python /C /Perl /Shell / UVM Verilog and System Verilog Good understanding of the...

28 Sep
Design Verification Engineer
Location: Markham, ON
Salary: N/A

and directed) using System Verilog/UVM/SystemC Triaging and Debugging Regressions Analyzing code and functional coverage... Proficient in Verilog, System Verilog, C/C++, UVM, OOP, and working in Linux and Windows environments ASIC design knowledge...

28 Sep
SoC Design Verification Engineer
Location: Markham, ON
Salary: N/A

components, and test-cases Generate and verify test sequences PREFERRED EXPERIENCE: Knowledge of Verilog or SystemVerilog...

28 Sep
SoC Design Verification Engineer
Location: Markham, ON
Salary: N/A

components, and test-cases Generate and verify test sequences PREFERRED EXPERIENCE: Knowledge of Verilog or SystemVerilog...

28 Sep
RTL Design Engineer
Location: Markham, ON
Salary: N/A

closure(e.g. Formality, CDC & Linting tools, Design Compiler/FX etc) Strong background in Verilog and System Verilog...

27 Sep
SoC Verification Engineer
Location: Markham, ON
Salary: N/A

PERSON: Define verification plans for SoC designs using System Verilog with UVM and C++/DPI. Integrate verification IPs...

27 Sep
SoC Verification Engineer
Location: Markham, ON
Salary: N/A

those plans. THE PERSON: Define verification plans for SoC designs using System Verilog with UVM and C++/DPI. Integrate...

27 Sep
Design Verification Engineer
Location: Markham, ON
Salary: N/A

and directed) using System Verilog/UVM/SystemC Triaging and Debugging Regressions Analyzing code and functional coverage... Proficient in Verilog, System Verilog, C/C++, UVM, OOP, and working in Linux and Windows environments ASIC design knowledge...