Found 98 jobs on 10 pages

15 Feb
CPU-SoC Silicon Design Engineering Part Time Intern
Location: Pulau Pinang
Salary: N/A

, SOC/PC Architecture, System Verilog is major plus Inside this Business Group The Client Computing Group (CCG...

13 Feb

verification/logic design including but not limited to: System Verilog, PERL/C/C++ programming, Synopsys simulator will be big...

13 Feb
Design Verification Intern
Location: Pulau Pinang
Salary: N/A

. PREFERRED EXPERIENCE: Advanced knowledge of ASIC Design flow and state of the art verification flow Proficient with Verilog..., System Verilog and UVM Familiarity with industry standard high-speed protocols such as PCIE is a plus Strong analytical...

12 Feb
FPGA Engineer
Location: George Town, Pulau Pinang
Salary: 4000 - 5000 per month

-Develop, maintain, and optimize HDL testbenches using System Verilog/VHDL -Collaborate with hardware design teams... with EDA tools and simulation environments -Proficiency in HDL (VHDL/Verilog),C++, Python 2/3 -Advanced knowledge of Python...

09 Feb
Design Verification Engineer (Junior& Senior)
Location: Malaysia
Salary: 4000 - 12000 per month

experience The candidate should have good understanding on ASIC/SOC design flow and should have: 1. Strong coding with Verilog...

09 Feb
IP Design Verification Engineer
Location: Pulau Pinang
Salary: N/A

candidates. Minimum Qualifications: System Verilog (primary), OVM/UVM (primary), Verilog Testbench, Logic Design/RTL Design, Good...

08 Feb
Senior Staff Emulation Engineer
Location: Pulau Pinang
Salary: N/A

communication skill Experience with FPGA and/or emulation platforms Experience in developing System Verilog based test content...

08 Feb
Formal Verification Engineer
Location: Pulau Pinang
Salary: N/A

: Research in formal verification domain RTL languages like System Verilog or VHDL Assertion languages like SVA. Preferred...

08 Feb
Formal Verification Engineer
Location: Pulau Pinang
Salary: N/A

experience in the following : Research in formal verification domain RTL languages like System Verilog or VHDL Assertion...

07 Feb
Graduate Talent (IP System Validation)
Location: Pulau Pinang
Salary: N/A

architecture, logic verification with a good understanding of logic design concepts. Verilog, SystemVeri log. RTL simulation...