Found 17 jobs on 2 pages

25 Dec
Design Verification Engineer
Location: Cork
Salary: €50000 - 90000 per year

such as bugs and coverage. Required Skills and Experience: Proficiency in SystemVerilog, UVM, Verilog, VHDL, and C/C...

14 Dec
Principal Design Engineer
Location: Cork
Salary: N/A

: processor design, on-chip communication and interconnects, high-speed interfaces, or chiplets. Expertise in Verilog/System... Verilog for coding and verification. Proficiency in RTL design techniques, including synthesis, timing closure...

14 Dec
Principal Design Engineer
Location: Cork
Salary: N/A

: processor design, on-chip communication and interconnects, high-speed interfaces, or chiplets. Expertise in Verilog/System... Verilog for coding and verification. Proficiency in RTL design techniques, including synthesis, timing closure...

14 Dec

or compiler experience is a plus Verilog/Vera/System Verilog experience is a plus Where you will be working Cork...

11 Dec
FY25 Graduate Digital Design Engineer
Location: Cork
Salary: N/A

in Cork, this position will involve many of the following tasks. Architectural design and specification of blocks. Verilog..., in Engineering (Electronic Engineering) or equivalent Design, Coding and Scripting experience: Verilog/systemVerilog, C/C++, Python...

11 Dec
GPU Modelling Engineer - Cork, Ireland
Location: Cork
Salary: N/A

is a plus Verilog/Vera/System Verilog experience is a plus Where you will be working Cork has a proud reputation as Ireland...

27 Nov

required Computer Architecture, Digital Design, Coding and Scripting: Verilog, C/C++, Python, Tcl/Perl/shell-scripting. Verification... Methodology using System Verilog. Knowledge of Low Power Design. Knowledge of ARM processors or RISC-V processors architecture...

23 Nov
Staff Mixed-Signal DV Engineer
Location: Limerick
Salary: N/A

) and behavioral modeling (SystemVerilog RNM, Verilog-AMS, Verilog-A) is a plus. Should be able to communicate technical details very...

20 Nov

of scalable design consideration Clock domain crossing design experience RTL writing skills in Verilog/SystemVerilog Scripting...

20 Nov

environment and flow build-up with UVM, Coverage-Driven verification methodology Experienced with Assertions like System Verilog... coverage goals Extensive usage of RTL simulation tools. UVM, System Verilog, Perl/Python shell-scripting skills...