Found 125 jobs on 13 pages

27 Mar

der digitalen Nachrichtenübertragung und Signalverarbeitung Erfahrung in der Programmierung von FGPA’s mit VHDL / Verilog...

27 Mar
FPGA Developer (m/f/d) - 100% on-site
Location: Heidelberg, Baden-Württemberg
Salary: N/A

: Verilog, System Verilog, UVM Scripting Language (z.B. TCL, Python) Mentor ModelSim/QuestaSim Xilinx ISE/Vivado... und / oder MicroSemi Libero DOORS und / oder JAMA High-Level-Synthese SVN/Clearcase Windows/Linux (User, Scripting) Verilog, System...

24 Mar
Senior Digital Design Engineer (m/f/d)
Location: Freiburg, Baden-Württemberg
Salary: N/A

and the corresponding design tools. Deep knowledge and experience of: - hardware description languages (Verilog, System... Verilog, VHDL) - script languages (TCL, Python, etc.) - standard digital design flow (RTL-coding, design compiler, logic...

22 Mar
AMS Design Verification Engineer (m/f/d)
Location: München, Bayern
Salary: N/A

Qualifications Key Qualifications Knowledge of System Verilog test-bench language and UVM (Universal Verification Methodology...) Familiarity with system design using C (C++) or Verilog is a plus ATE functional test pattern generation for logic testers...

22 Mar

. Verification planning and management experience with block level and top-level designs. Experience with HDL coding (VHDL/Verilog.../System Verilog) and UVM. Expertise in clock/reset and low power design & verification techniques. Experience with Linux...

22 Mar
FPGA Verification & Validation Engineer (f/m/d)
Location: Heidelberg, Baden-Württemberg
Salary: N/A

Components. System Verilog Sequence Development Developing DO254 related documents including but not limited to: Test Plans... Graphics Questasim Verilog VHDL Our Benefits Unlimited employment with individual training and development opportunities...

21 Mar
Senior Staff Engineer Analog Design (f/m/div)
Location: München, Bayern
Salary: N/A

Verilog-A zur Modellierung der analogen Schaltungsblöcke Kenntnisse in Verilog / Systemverilog zur Beschreibung von...

21 Mar
Efficiently Porting ASIC Flows for FPGA Prototyping
Location: München, Bayern
Salary: N/A

's degree in Computer Science or equivalent Knowledge of Object Oriented Programming Knowledge of Verilog and/or VHDL (FPGA...

17 Mar
Senior Staff Engineer Digital Verification (f/m/div)
Location: München, Bayern - Bristol Area
Salary: N/A

Testbenches for Complex Digital Circuits based on System Verilog/UVM Translate Design Specifications into Verification Plans... digital circuits Strong experience with constrained random verification using System Verilog Solid know-how in simulation...

16 Mar
Senior/Principal Digital Methodology Engineer
Location: Germering, Bayern
Salary: N/A

languages (Verilog and System Verilog) Expert with Unix/Linux Environments Expert in Logic Synthesis, Design for Test, Static...