Found 15 jobs on 2 pages

27 Jun

At least 5 years of hands-on experience in digital design Expertise in Verilog and SystemVerilog for RTL design Proficiency...

24 Jun

Requirements specification in formal tools (e.g. Intland Codebeamer) Digital IC front-end design implementation using Verilog... (Verilog, System-Verilog, VHDL, Synthesis, LINT) is a plus Experience with advanced MCU/bus-system based digital architectures...

16 Jun

! Do you bring experience with Unix programming languages as well as knowledge of VHDL, Verilog and C? Then we should get to know... or Telematics with focus on electronics Good knowledge of VHDL, Verilog, C Good knowledge of Unix programming languages...

15 Jun

of VHDL, Verilog, C Good knowledge of Unix programming languages such as Shell, Perl, TCL etc. Fluent English skills, German...

14 Jun
Universitätsassistent_in (Prae-Doc)
Location: Vienna
Salary: €2684.1 per month

im Bereich des Entwurfs integrierter Schaltungen mit FPGAs und ASICs, VHDL oder Verilog Interesse insbesondere auf dem Gebiet...

09 Jun
Staff Digital Design Engineer (f/m/d)
Location: Graz, Steiermark
Salary: N/A

understanding of advanced verification methodologies (e.g. OVM, ABV) Fluent in either Verilog or VHDL RTL coding and ASIC design...

02 Jun
Staff Digital Design Engineer (f/m/d)
Location: Graz, Steiermark
Salary: N/A

either Verilog or VHDL RTL coding and ASIC design methodology. Proven ability to optimize and develop design architecture from chip...

31 May
Junior Digital Verification Engineer (m/f/d)
Location: Gratkorn, Steiermark
Salary: N/A

. Your profile: University Degree in Electrical/Electronic Engineering, Computer Science or equivalent; Proficiency in Verilog... and System Verilog languages (VHDL is a plus) Experience in test-bench design and development in UVM; Understanding...

30 May
Lead Principal Engineer Digital Design (f/m/div)
Location: Graz, Steiermark
Salary: N/A

SystemVerilog and / or Verilog / VHDL for RTL design and verification tasks Proficiency in scripting languages like Python or Perl...

29 May
Lead Principal Engineer Digital Design (f/m/div)
Location: Graz, Steiermark
Salary: N/A

) to manage power intent in the design Proficiency in SystemVerilog and / or Verilog / VHDL for RTL design and verification tasks...