Found 14 jobs on 2 pages

15 May
Senior R&D engineer (FPGA Developer) @ Hitachi Energy
Location: Krakow, Malopolskie
Salary: N/A

/ASIC design & simulation in VHDL/(and/or Verilog) - 5 years for Senior, 5-10 for Senior II Good understanding... and the business. ] Requirements: Degree, FPGA, VHDL, Verilog, Prototyping, Testing, Communication skills...

15 May
Principal R&D Engineer - FPGA Developer @ Hitachi Energy
Location: Krakow, Malopolskie
Salary: N/A

of experience of FPGA/ASIC design & simulation in VHDL/(and/or Verilog). Good understanding of synchronous design, time... business.] Requirements: Degree, FPGA, VHDL, Verilog, Prototyping, Testing, Communication skills...

09 May
R&D Engineer - FPGA Developer
Location: Krakow, Malopolskie
Salary: N/A

VHDL/(and/or Verilog) Good understanding of synchronous design, time constraining and static timing analysis Experience...

09 May
Principal R&D Engineer - FPGA Developer
Location: Krakow, Malopolskie
Salary: N/A

VHDL/(and/or Verilog). Good understanding of synchronous design, time constraining and static timing analysis. Experience...

09 May
Senior R&D Engineer - FPGA Developer
Location: Krakow, Malopolskie
Salary: N/A

/(and/or Verilog) - 5 years for Senior, 5-10 for Senior II Good understanding of synchronous design, time constraining and static...

09 May
Staż - IT and Technology
Location: Krakow, Malopolskie
Salary: N/A

, elektronika, elektrotechnika, wiedza o systemach wbudowanych, wiedza o układach FPGA, znajomość VHDL lub Verilog, inżynieria...

09 May
R&D Project Manager (Embedded and SAFe experience)
Location: Krakow, Malopolskie
Salary: N/A

is an extra plus if you also have experience or knowledge from FPGA development (VHDL or Verilog) or hardware development...

03 May
RTL Design Engineer
Location: Krakow, Malopolskie
Salary: N/A

English, Experience in ASIC/SoC front-end design with RTL Verilog and VHDL, Previous exposure to SoC integration... and processor-based architectures, Proficiency in design and verification languages: VHDL, Verilog, C, and System Verilog...

03 May
Lead Design Verification Engineer
Location: Krakow, Malopolskie
Salary: N/A

. If you have expertise in SOC and IP verification, along with proficiency in System Verilog and UVM development, we want to hear... bench development, Building test bench environment in System Verilog using UVM methodology, Create IP and system...

03 May
Design Verification Engineer
Location: Krakow, Malopolskie
Salary: N/A

. If you have expertise in SOC and IP verification, along with proficiency in System Verilog and UVM development, we want to hear... Engineering or a related field, 3-8 years' experience in a similar role, Fluency in English, System Verilog using UVM...