Found 9 jobs on 1 pages

02 May
Analog Design, Engineer
Location: Yerevan
Salary: N/A

. Knowledgeable in Verilog-A for analog behavioral modeling and simulation-control/data-capture. Experience with TCL, Perl, C, Python...

01 May
Applications Engineering, Engineer
Location: Yerevan
Salary: N/A

. Minimum Requirements Knowledge of one digital design language such as Verilog, VHDL or SystemVerilog Understanding of digital design...

13 Apr
ASIC Digital Design, Sr Engineer
Location: Yerevan
Salary: N/A

Familiarity with Verilog/System Verilog Familiarity with FPGA Good understanding of Digital Design flow Good knowledge...

28 Mar
Intern (Technical-Engineering)
Location: Yerevan
Salary: N/A

, LIB, Verilog, etc.) Understanding of the analog and digital design flows Basic knowledge of Synopsys tools is an asset...

13 Mar
Applications Engineering, Staff Engineer
Location: Yerevan
Salary: N/A

digital design using Verilog or System Verilog Familiarity with some of the industry-standard protocols will be a plus (AMBA...

09 Mar
ASIC Digital Design, Staff Engineer
Location: Yerevan
Salary: N/A

degree in Electrical Engineering Exposure to Verilog, System Verilog or VHDL Exposure to Unix, Perl, and TCL scripting...

01 Mar
ASIC Digital Design, Engineer
Location: Yerevan
Salary: N/A

. Key Requirements: Relevant degree in Electrical/Electronic Engineering or equivalent Exposure to Verilog, System... Verilog or VHDL Exposure to Unix, Perl, and TCL scripting Knowledge of MIPI or similar protocols would be advantageous Good...

23 Feb
ASIC Physical Design, Staff Engineer
Location: Yerevan
Salary: N/A

, implementation flows and sign-off methodologies for deep submicron design. Knowledge of industry standard data file formats: Verilog...

22 Feb
ASIC Physical Design, Engineer
Location: Yerevan
Salary: N/A

submicron design. Knowledge of industry standard data file formats: Verilog, GDS, LEF, DEF, SDF, LIB, UPF, CPM, CMM. Scripting...