Showing page 4 of 5 (Total listings: 83)

FPGA Digital Design Engineer

Universal Quantum ✓ Verified
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Haywards Heath, West Sussex
Tue, 01 Sep 2026 02:35:04 GMT

. Experience in HDL design and verification using Verilog, VHDL or System Verilog. Use of spectrum analysers, oscilloscopes

Lead FPGA Development Engineer

GE Vernova ✓ Verified
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Stafford, Staffordshire
Tue, 01 Sep 2026 01:56:19 GMT

in FPGA design and development, using VHDL, Verilog or equivalent HDL technologies. Strong understanding of digital

Electronics Engineer

Sagentia ✓ Verified
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Cambridge
Sat, 29 Aug 2026 00:51:43 GMT

beneficial to this role FPGA hardware design experience including VHDL / Verilog programming. Simulation of designs using

Embedded Software Engineer

Daintta ✓ Verified
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London
Fri, 28 Aug 2026 00:49:36 GMT

Experience with FPGAs including development using VHDL or Verilog Experience with RF, including SDRs Location? Hybrid

Embedded Software Engineer

Daintta ✓ Verified
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London
Thu, 27 Aug 2026 22:45:20 GMT

Experience with FPGAs including development using VHDL or Verilog Experience with RF, including SDRs Location? Hybrid

Principal Modelling Engineer

Nexperia ✓ Verified
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Manchester
Wed, 26 Aug 2026 06:30:45 GMT

, device structures, and their interactions Experience with Compact SPICE modelling, Verilog-A, and VHDL-AMS Hands

FPGA Engineer

IC Resources ✓ Verified
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United Kingdom
Wed, 26 Aug 2026 05:18:42 GMT

with the following background: 2+ years of commercial FPGA/RTL development experience RTL coding using Verilog or VHDL

Principal FPGA Engineer

Fintec Recruit ✓ Verified
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Edinburgh
Wed, 26 Aug 2026 00:13:03 GMT

technology projects in a collaborative, technically skilled environment. Key focus: FPGA design, VHDL / Verilog development..., Verilog, SystemVerilog and/or relevant methodologies. Working with Systems, Hardware and Software teams to support

Digital Design Engineer

SoCode ✓ Verified
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Cambridge
Tue, 25 Aug 2026 01:53:42 GMT

platforms (Verilog or VHDL) Strong grasp of fixed-point DSP techniques - think filters, FFT implementations, correlators Hands

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Kidlington, Oxfordshire
Tue, 18 Aug 2026 02:18:16 GMT

, software, and physics teams. Desirable Core Requirements FPGA development experience using VHDL or Verilog on Xilinx FPGAs

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Kidlington, Oxfordshire
Mon, 17 Aug 2026 22:12:34 GMT

teams. Desirable Core Requirements FPGA development experience using VHDL or Verilog on Xilinx FPGAs. Experience

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Cambridge
Mon, 17 Aug 2026 03:20:53 GMT

is required for Staff level. -Working knowledge of Verilog-AMS modelling, MATLAB and Python is a bonus. Familiar with the use

Low Latency MM Engineer

G-20 Group ✓ Verified
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London
Fri, 14 Aug 2026 22:41:20 GMT

Experience with FPGA development (Verilog/VHDL) is advantageous, though not a strict requirement for all candidates Demonstrated

Staff FPGA Engineer

IC Resources ✓ Verified
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Oxfordshire
Fri, 14 Aug 2026 05:08:41 GMT

: 10+ years of hands-on FPGA development experience Strong RTL design and verification using SystemVerilog, Verilog

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Lausanne - London
Fri, 14 Aug 2026 03:40:02 GMT

, communication systems, high-speed digital interfaces, and payload data path architecture. Proficiency with VHDL, Verilog

Contract FPGA Engineer

Redline Group ✓ Verified
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Milton Keynes
Tue, 11 Aug 2026 07:17:34 GMT

working with more than one language - VHDL, Verilog, SystemVerilog The successful Candidate must currently hold or be able

Electronics Design Engineer

BAE Systems ✓ Verified
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Guildford, Surrey
Tue, 11 Aug 2026 04:40:02 GMT

, ARM processors, GPUs and microcontrollers (typically using VHDL or Verilog) Designing signal processing algorithms

Staff Design Verification Engineer

Advanced Micro Devices ✓ Verified
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Cambridge
Mon, 10 Aug 2026 23:52:09 GMT

and firmware using industry-standard simulation tools. Experience with Verilog, SystemVerilog, C, and C++. Experience developing

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Cambridge
Sat, 08 Aug 2026 06:44:21 GMT

and memory subsystems Knowledge of Verilog and/or VHDL. Experience with simulators and waveform debugging tools Knowledge

FPGA Electronics Engineer - Defence

Newton Colmore Consulting ✓ Verified
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Cambridge
Thu, 06 Aug 2026 23:12:16 GMT

or advanced communications technologies. Strong experience with VHDL or Verilog is essential, and any exposure to areas

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