ASIC Design Engineer
and implement ASIC architectures Designs and develops RTL code using SystemVerilog and Verilog Conducts design verification... and methodologies Proficient in SystemVerilog, Verilog, and RTL Design Possesses familiarity with security-related applications
Staff Verification Engineer
as mandatory and Subsystem level as an advantage Expertise in hardware verification languages, particularly System Verilog and UVM
Principal Staff Verification Engineer
hands-on experience in block-level/IP-level/SoC-level verification Proficiency in Verilog, SystemVerilog Familiarity
Senior Design Verification Engineer
verification process applied in CPU and/or ASIC environments System Verilog, Python, C++, Linux UVM SVA LLVM, GCC SGE
FPGA Design Engineer
. Responsibilities Design, develop, and verify RTL code in SystemVerilog, Verilog, VHDL and/or Migen for Xilinx Zynq and Ultrascale... in SystemVerilog, Verilog and/or VHDL with a solid understanding of RTL design principles. Hands-on experience with Xilinx or Altera
Principal Firmware Engineer Level 6
and stakeholder engagement skills within multidisciplinary teams. Desirable Skills VHDL, Verilog, SystemVerilog, and UVM
FPGA Engineer
Engineer with the following background: FPGA development experience using VHDL, Verilog, or SystemVerilog Experience
DFT & Post-Silicon Validation
SystemVerilog and Verilog. Strong scripting skills (Shell, Tcl, Python3). Hands-on experience with Tessent and SSN methods
DFT & Post-Silicon Validation
SystemVerilog and Verilog. Strong scripting skills (Shell, Tcl, Python3). Hands-on experience with Tessent and SSN methods
DFT & Post-Silicon Validation
SystemVerilog and Verilog. Strong scripting skills (Shell, Tcl, Python3). Hands-on experience with Tessent and SSN methods
DFT & Post-Silicon Validation
SystemVerilog and Verilog. Strong scripting skills (Shell, Tcl, Python3). Hands-on experience with Tessent and SSN methods
Senior FPGA Engineer
. They are looking for a Senior FPGA Engineer with the following background: Strong FPGA development experience using VHDL, Verilog, or SystemVerilog
FPGA Engineer
Proficiency in design tools such as Verilog, System Verilog, and UVM Experience with Siemens tools like HDL Designer
DFT & Post-Silicon Validation
SystemVerilog and Verilog. Strong scripting skills (Shell, Tcl, Python3). Hands-on experience with Tessent and SSN methods
DFT & Post-Silicon Validation
SystemVerilog and Verilog. Strong scripting skills (Shell, Tcl, Python3). Hands-on experience with Tessent and SSN methods
Digital Design Engineer (AP)
Implementation of complex digital circuits and sub-systems in RTL using Verilog / SystemVerilog Understanding of digital system
Senior / Principal FPGA Engineer
and development of FPGA designs using VHDL and verifying designs using VHDL or System Verilog. Job Responsibilities: The FPGA... of developing FPGA using VHDL or Verilog Experienced with Mentor Graphics FPGA development tools including HDL Designer, ModelSim
Analog IC Design Engineer
modelling (Verilog-AMS, SystemVerilog or equivalent) Understanding of DFM, yield optimisation, and semiconductor reliability
Lead Engineer
individual in this role needs to have strong FPGA design experience. VHDL experience preferred, Verilog experience acceptable
Principal Analog IC Design Engineer
modelling (Verilog-AMS, SystemVerilog). Familiarity with optoelectronic components such as PIN diodes, lasers, and Mach-Zehnder