Principal ASIC Design Engineer
Verilog/SystemVerilog expertise Solid understanding of industry-standard EDA tools and design methodologies Deep knowledge
CPU ASIC Design Engineer
Proficiency in Verilog and/or VHDL Solid grounding in logic design, timing closure, and power optimisation Knowledge of low
Staff Digital Design Engineer
within one of the UK’s strongest semiconductor hubs Key experience 10+ years’ experience in Digital IC/SoC Design Strong Verilog
FPGA Electronics Engineer - Defence
or advanced communications technologies. Strong experience with VHDL or Verilog is essential, and any exposure to areas
Mixed Signal Verification Engineer
development. Behavioral modeling of analog blocks, System Verilog Real-Number Modeling, model validation. Knowledge of Cadence
FPGA Design Engineer
Verilog\UVM test-bench methodologies. Using FPGA design toolsets and Mentor verification tools (QuestaSim & ModelSim
Principal Analog IC Design Engineer
techniques Understanding of DFM, reliability, and yield optimisation Experience with behavioural modelling (Verilog-AMS
Senior Staff Verification Engineer (f/m/div)
of complex IP verification, developing System Verilog - UVM test bench environments Create functional coverage models and write...+ years of experience in Verification Engineering, with hands-on exposure to System Verilog - UVM (academic, internship