Low Latency MM Engineer
Experience with FPGA development (Verilog/VHDL) is advantageous, though not a strict requirement for all candidates Demonstrated
ASIC Design Engineer, Amazon Camera ASIC Team
-architectural specs which work through the design problems before coding (System Verilog, Verilog). Preferred Qualifications
ASIC Verification Engineer, Amazon Camera ASIC Team
to system level - Proficiency in System Verilog - Experience in identifying and resolving complex design and verification... tools and scripting languages (Python or Perl) for automation - System Verilog coding and debug Amazon is an equal
Lead Firmware Engineer
, Microsemi (Actel) or Lattice and their tools. Advancedverification techniquesusing eitherVHDLorSystem Verilog/ UVM. Specifying
Staff FPGA Engineer
: 10+ years of hands-on FPGA development experience Strong RTL design and verification using SystemVerilog, Verilog
Hardware Engineer
, ideally up to SIL4. Hands-on experience with modern microcontroller SDKs. Knowledge of FPGA design (VHDL/Verilog) and CPLD
Hardware Engineer
, ideally up to SIL4. Hands-on experience with modern microcontroller SDKs. Knowledge of FPGA design (VHDL/Verilog) and CPLD
Contract FPGA Engineer
working with more than one language - VHDL, Verilog, SystemVerilog The successful Candidate must currently hold or be able
Electronics Design Engineer
, ARM processors, GPUs and microcontrollers (typically using VHDL or Verilog) Designing signal processing algorithms
Staff Design Verification Engineer - Edinburgh/Cambridge
and firmware using industry-standard simulation tools. Experience with Verilog, SystemVerilog, C, and C++. Experience developing
Senior Design Engineer
using Verilog or SystemVerilog Experience designing complex digital IP, SoCs or CPU subsystems Knowledge of on-chip
Senior Staff Software Development Engineer
systems Experience of digital design (EDA tools, Verilog, VHDL) ACADEMIC CREDENTIALS: Bachelor’s, Master's or PhD
Principal FPGA Engineer
design/architecture Verification Test bench architecture with System Verilog or C++ Verification Methodology: Advanced...: Mentor Graphics Modelsim / Questasim Digital electronic design in hardware development languages: VHDL and either Verilog
Principal Firmware Engineer
and forward-thinking approach. Skills & Experience We Value Familiarity with Verilog/SystemVerilog, OSVVM, UVM or UVVM
Principal Engineer Digital Design (f/m/div)
synthesis, STA, UPF (low power design) and DfT Proficiency in HDLs like System Verilog or VHDL Strong know-how in C
CPU RTL Design Engineer (Senior/Staff) - Cambridge, UK
and memory subsystems Knowledge of Verilog and/or VHDL. Experience with simulators and waveform debugging tools Knowledge
Principal FPGA Engineer
design/architecture Verification Test bench architecture with System Verilog or C++ Verification Methodology: Advanced...: Mentor Graphics Modelsim / Questasim Digital electronic design in hardware development languages: VHDL and either Verilog
FPGA Engineer
Engineer with the following background: Strong FPGA development experience using VHDL, Verilog, or SystemVerilog Experience
FPGA Electronics Engineer - Defence
or advanced communications technologies. Strong experience with VHDL or Verilog is essential, and any exposure to areas
Security Researcher
such as VHDL or Verilog. Fundamental understanding of digital and wireless communications, cellular architectures, mobile network