ASIC Technical Lead
We're partnering with a cutting-edge medical technology company in San Diego that is looking for an experienced ASIC Technical Lead to take technical ownership of a highly sophisticated mixed-signal ASIC program. This is a unique opportunity to serve as the internal technical authority for a high-channel-count neural recording chip being developed with an external IC design partner. The role will be responsible for: • Owning ASIC requirements and technical specifications • Leading design and ar…
ASIC Design Engineer
Principal Duties & Responsibilities: • Leverages advanced ASIC knowledge and experience to define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC) development for a variety of high performance, high quality, low power products. • Creates advanced architectures, circuit specifications, logic designs, and/or system simulations based on system-level requirements. • Collaborates across functional teams (e.g., software architecture, hardware …
ASIC DFT Engineer
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ASIC Physical Design
Role -ASIC Physical Design Location: San Jose, CA (onsite) Job Type- W2 Contract Interview Process: 1 phone, 1 panel onsite (zoom option) Skills/JD: Physical Design engineer to own the entire block Floorplanning, PlacenRoute, Timing Closure DRC/LVS checks Low nm experience preferred Cadence tooling - They are using Innovus and Voltus mostly Synopsys tools for Timing Analysis job requirements below: Good understanding of Cadence tools (Innovous, Quantus, Voltus). Deep knowledge about industry st…
Senior ASIC Physical Design Engineer
As a Senior ASIC Physical Design Engineer, you will execute synthesis, place-and-route, and static timing analysis for SoC partitions, working closely with RTL, architecture, and DFT teams. You will resolve timing, EM/IR, and physical verification issues, drive block-level signoff, refine implementation methodologies, and troubleshoot EDA flows in advanced sub-7nm technologies in an on-site environment. Execute synthesis, place-and-route (PnR), and static timing analysis for assigned ASIC parti…
ASIC Synthesis and DFT CAD Engineer
Qualcomm seeks a Synthesis-DFT Stitch CAD Engineer to develop and optimize digital implementation flows for advanced wireless SoCs. You will own synthesis, scan insertion, and DFT stitching for large, multi-clock designs, building robust, automated CAD flows that scale across projects and process nodes. Partner with front-end, physical design, and test teams to refine constraints, close timing, and improve test coverage. Analyze tool reports, debug complex implementation issues, and drive metho…
ASIC Verification Engineer
ASIC Verification Engineer Santa Clara, CA 12 Months $75 - $80/HR Role: Lead block-level functional verification for complex CPU/GPU SoCs using directed and constrained-random simulation. Must Have: 5-7 years experience, expert C/C++ in Linux, OOP/STL, and Verilog/SystemVerilog (Formal Verification / 7 years preferred). Dexian stands at the forefront of Talent Technology solutions with a presence spanning more than 70 locations worldwide and a team exceeding 10,000 professionals. As one of th…
Senior ASIC Verification Engineer
Pay Range: $104.47hr - $110.27hr Job Overview: The candidate will participate in the functional verification of a block(s) of complex ASICs and/or IP cores for a combined CPU/GPU development effort. As part of a team of design and verification engineers, the successful candidate will work closely with other team members to understand and verify the functionality of a given design element within the context of the block, chip and overall system. The candidate will be responsible for carefully do…
ASIC/SoC Physical Design Engineer II
Arrow Electronics is seeking a Physical Design Engineer II to drive advanced IC implementation for customers in the wholesale technology ecosystem. In this role, you will execute full physical design flows for ASIC/SoC projects, including floorplanning, place-and-route, CTS, STA, and sign-off. You will collaborate with global design, verification, and architecture teams to meet performance, power, and area targets. This position offers exposure to cutting-edge EDA tools, complex designs, contin…
ASIC/SoC Physical Design Engineer II
Arrow Electronics is seeking a Physical Design Engineer II to drive advanced IC implementation for customers in the wholesale technology ecosystem. In this role, you will execute full physical design flows for ASIC/SoC projects, including floorplanning, place-and-route, CTS, STA, and sign-off. You will collaborate with global design, verification, and architecture teams to meet performance, power, and area targets. This position offers exposure to cutting-edge EDA tools, complex designs, contin…
ASIC Engineering Technical Leader
SDH Systems is hiring ASIC Engineering Technical Leader with Min 12 Years of experience with a focus on Design-for-Test and can lead the development of DFT solutions for next-generation ASICs for multi-100G to 1.6T coherent optical communications products. Job Title: ASIC Engineering Technical Leader Location: San Jose , CA Interview Process: Video Work Schedule: Onsite Job Description: We are seeking a motivated, proactive, and intellectually curious ASIC Engineering Technical Leade r with a f…
Senior ASIC Emulation Engineer
Our Mission At Palo Alto Networks , we're united by a shared mission-to protect our digital way of life. We thrive at the intersection of innovation and impact, solving real-world problems with cutting-edge technology and bold thinking. Here, everyone has a voice, and every idea counts. If you're ready to do the most meaningful work of your career alongside people who are just as passionate as you are, you're in the right place. Who We Are In order to be the cybersecurity partner of choice, we …
ASIC Engineering Technical Leader
Role: ASIC Engineering Technical Leader Location: San Jose, CA (Onsite) Start Date: Immediate Type: Contract (C2C/W2) Interview: Phone/Video We are seeking an ASIC Engineering Technical Leader with strong expertise in DesignforTest (DFT) for nextgen optical communication ASICs. Responsibilities include DFT architecture implementation, scan insertion, ATPG pattern generation, silicon debug, integration/verification of DFT fabrics, gatelevel simulations, and automation using Python/Tcl/C++ . Qual…
ASIC Design Verification Engineer
Job Details ASIC Design Verification Engineer 12 Months Contract with Possible Extension Austin, TX & Menlo Park, CA Job Summary We are seeking a highly motivated ASIC Design Verification Engineer to join our silicon engineering team. The ideal candidate will have strong experience in SystemVerilog/UVM-based verification of complex IPs or SoCs and will be responsible for developing test cases, debugging RTL issues, and driving coverage closure. Responsibilities Maintain reusable SystemVerilog/U…
ASIC Design Verification Engineer
Job Details ASIC Design Verification Engineer 12 Months Contract with Possible Extension Austin, TX & Menlo Park, CA Job Summary We are seeking a highly motivated ASIC Design Verification Engineer to join our silicon engineering team. The ideal candidate will have strong experience in SystemVerilog/UVM-based verification of complex IPs or SoCs and will be responsible for developing test cases, debugging RTL issues, and driving coverage closure. Responsibilities Maintain reusable SystemVerilog/U…
ASIC Physical Design Engineer
We’re hiring for a full-time opportunity with a leading semiconductor end client in Lafayette, IN. Seeking experienced ASIC Physical Design / Backend Engineers with strong TSMC FinFET tapeout and signoff experience Detailed job description is given below. Title: ASIC Physical Design Engineer (TSMC / FinFET) Location: Lafayette, Indiana ( “Relocation assistance provided”) Type: Full time with Client Tapeout , Signoff , DRC/LVS/PEX, Customer interaction Job Responsibilities: Act as the primary in…
Principal ASIC Verification Engineer
Principal ASIC Verification Engineer San Jose, CA 6 Months $95 - $100/HR Role: Lead block-level functional verification for complex CPU/GPU SoCs using directed and constrained-random testing. Must Have: 10 years experience, expert C/C++ in Linux environments, OOP/STL, debug tools (Gdb/Valgrind), and Verilog/SystemVerilog. Dexian stands at the forefront of Talent Technology solutions with a presence spanning more than 70 locations worldwide and a team exceeding 10,000 professionals. As one of …
ASIC Physical Design Engineer (Hybrid)
Mentium Technologies Inc. is seeking an experienced and highly motivated Physical Design Engineer to join our ASIC/SoC design team. In this role, you will be responsible for the physical implementation of complex ASIC designs from synthesis through place and route, DRC/LVS and tapeout. You will work closely with RTL designers, architects and OSAT, foundry partners to ensure high-quality, timing-clean, and manufacturable silicon. This role offers an exciting opportunity to learn and work on cutt…
Sr. ASIC DFT Engineer (Silicon)
SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars. SR. ASIC DFT ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building rockets and spacecraft to deploy Starlink, the world's most advanced broadband internet system. Starlink is the world's …
Sr. ASIC DFT Engineer (Silicon)
SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars. SR. ASIC DFT ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building rockets and spacecraft to deploy Starlink, the world's most advanced broadband internet system. Starlink is the world's …