Senior Source-Code Reviewer (Patent Litigation) Part-Time
Senior Source-Code Reviewer (Patent Litigation) Part-Time Location: Remote / Austin, TX Type: Part-Time (Project-Based) Key Responsibilities Deep Dive Code Review: Analyze complex codebases, focusing on firmware, drivers, and kernel-level C/C++. Hardware/Software Correlation: Review RTL (Verilog/SystemVerilog) and hardware schematics to map physical hardware behaviors (power rails, clocking, interfaces) to software execution. Litigation Analysis: Identify and document specific code modules and …
Verification Consultant
6 months Start Date – August 31 Austin, TX (onsite) – San Jose can be an option for perfect candidate Pay Rate - $93/hr Must Be W-2 Must Have: Gate Level Simulation Ownership is most important….needs to have this experience. UVM/System Verilog Experience High performance computing background would be a huge …someone from AMD, Qualcomm, etc AXI/CHI protocols Position Details Vertical Description Technical As a Senior Staff System IP Design Verification Contractor you will contribute to the funct…
Staff FPGA Engineer with Security Clearance
Overview VTG is seeking a Staff FPGA (Field Programmable Gate Array) Engineer to support our Defense customer in Reston, VA. Our Staff FPGA Engineer will be responsible for rapidly developing, testing, and implementing FPGA designs on Xilinx SoC/FPGA platforms. This requires strong skills in digital circuit design, VHDL/Verilog coding, and simulation to contribute to projects that are shaping the future of defense. What will you do? * Integrate third-party vendors IP, as necessary * Participate…
Opening for Design Verification Engineer, Principal - CA
We have opening for Design Verification Engineer, Principal Location - Santa Clara, CA Full time permanent position Sponsorship available Must-haves BS Computer Engineering, Electrical Engineering, or Computer Science 10 years of verification and firmware and software development experience (or MS/PhD 5 years experience). Proven track records of leading Design Verification implementation activity Tape-out of complex SOC under tight schedule. In depth understanding and experience with System Ver…
FPGA Engineer with Security Clearance
B. S. Degree in Electrical or Computer Engineer - may consider other Engineering degrees based on experience. 2 or more years experience in Electrical Engineering Looking for Firmware and hardware knowledge - a candidate that can look at a circuit and know what is going on. Must have a willingness to learn in a rapid paced environment FPGA (they use Xilinx) but any Internship or Co-Op experience with FPGAs but real world is ideal C-code or VHDL or Verilog experience helpful Microcontrollers exp…
FPGA/ASIC Design Engineer (US Citizen) - Camden, NJ - 4822 with Security Clearance
Important Notes: * VHDL Experience is required for all candidates to be considered. * Looking for mid-senior level folks We've determined which skillsets are most beneficial for this role. These skills are listed first below as the Must Haves and Nice to Haves our hiring team highly prefers. Below that you'll find the standard job description for this opportunity. Must Haves: * Proficient in VHDL >5 yrs, Xilinx FPGA design EDA- Vivado * Must have done hands on multiple complex designs arch/desi…
GPU Design Verification Engineer_Austin, TX/SanJose, CA(Onsite)_Only Xoriant W2
Xoriant is an equal opportunity employer. No person shall be excluded from consideration for employment because of race, ethnicity, religion, caste, gender, gender identity, sexual orientation, marital status, national origin, age, disability or veteran status. TITLE :- GPU Design verification Engineer LOCATION Austin, TX (Onsite) DURATION 6 Months (Will get extend) MODE OF INTERVIEW Onsite RATE As per market only Xoriant W2 (No Vendor employees) JOB DESCRIPTION We are looking for an experience…
Engineer Digital 3 with Security Clearance
Request ID: 1653 Title: Principal Digital Engineer Locations: Woodland Hills, CA 91367 Duration: 12 Months Contract with possible extension Rate Range: $90 - $100/Hour on W2 (All inclusive) Clearance Type: Active Secret clearance is required Overview: We are looking for you to join our team as a Principal Digital Engineer based out of Woodland Hills, CA. As a Principal Digital Engineer you will have a challenging and rewarding opportunity to be a part of our Enterprise-wide digital transformati…
FPGA Verification Engineer (SystemVerilog)
Title: FPGA Verification Engineer Location: Remote (One onsite visit to NY in the first few weeks, at client s expense for a week) Duration: 6-12 months Work Schedule: 9/80 or 5/8 Background or Drug Screen required: yes Project Details: Job Description: FPGA Verification Engineer Candidate will function in an FPGA verification role. Candidate will work in a cooperative team environment to verify and test embedded FPGA firmware for radio communication systems. Candidate will be required to analy…
ASIC & FPGA Design Engineer with Security Clearance
ASIC & FPGA Design Engineer Location: Grand Prairie, TX Job ID: 72890 Pay Range: $75-88 Job Description: You will be the Senior ASIC & FPGA Design Engineer for the Programmable Logic Design team. Our team creates, prototypes, and fields precision engagement aerospace and defense systems for the U.S. and allied militaries, delivering cutting edge digital solutions that protect the warfighter. What You Will Be Doing As the Senior ASIC & FPGA Design Engineer you will act as a technical leader on o…
Design Verification Engineer
Strong System Verilog/UVM knowledge with practical experience on live projects Expertise in AMBA bus protocols, ARM CPU, and experience in PCI Express and/or Ethernet bus protocols (desirable) · Proficiency in Unix, Configuration Management, Bug tracking, and verification dashboarding tools · Experience in developing functional verification environments, including components like monitors, checkers, scoreboards, and assertions, along with knowledge of verification methodologies using random sti…
ASIC & FPGA Design Engineering with Security Clearance
Chipton-Ross is seeking an ASIC & FPGA Design Engineer for a hybrid contract opportunity in Grand Prairie, TX. BASIC QUALIFICATIONS (REQUIRED SKILLS/EXPERIENCE) * Bachelor of Science degree in Electrical Engineering or a closely related STEM field from an accredited university; Master's degree preferred * Minimum 3 years of professional experience with FPGA design and simulation verification or a related discipline * Proficiency in HDL programming with VHDL, Verilog, and/or SystemVerilog * Expe…
Digital Engineer (FPGA/ ASIC)
Location: Los Angeles, CA Salary: $70.00 USD Hourly - $95.00 USD Hourly Description: Job Title: Digital Engineer (FPGA/ ASIC) Duration: 1 year (Possible extension or Perm) Location: About the Role We are looking for you to join our team as a Principal Digital Engineer based out of Woodland Hills, CA. As a Principal Digital Engineer you will have a challenging and rewarding opportunity to be a part of our Enterprise-wide digital transformation. Using Model-based Engineering, DevSecOps and Agile …
Principal Digital Engineer 3 with Security Clearance
Chipton-Ross is seeking multiple Principal Digital Engineer 3's for a contract opportunity in Woodland Hills, CA. BASIC QUALIFICATIONS (REQUIRED SKILLS/EXPERIENCE) * Bachelor's degree in a STEM field with 5 years of relevant experience; Master's degree in a STEM field with 3 years of relevant experience; PhD in a STEM field with 1 year of relevant experience * Experience with High-Speed Digital Design and Verification * Experience with FPGA/SOC/ASIC implementation (VHDL/Verilog, Synthesis, Timi…
Hardware Digital Engineer
hackajob is collaborating with Emerson to connect them with exceptional professionals for this role. Description Product R&D has an immediate opening for an entry-level Digital Hardware Engineer within our talented hardware design team in Austin, TX. In this role, you will have the opportunity to work throughout the product lifecycle to develop products and systems that expand the test and measurement industry's capabilities. Digital engineers at NI stand at the intersection of the many discipl…
Sr. Design Verification Engineer
Role: Senior Design Verification Engineer Location: San Jose, CA (Onsite) Experience: 7 Years What candidate will Be Doing: Strong expertise along with complex SoC/IP debug is a must At-least 5 years of experience in System Verilog HVL and C/C++. AMBA AXI bus along-with ARM or C based processor Experience in complete verification cycle which includes development of test plan, BFM/Driver/Monitor/Scoreboard component development and integration in test bench, stress/corner testing, failure debug,…
FPGA Engineer - Susquehanna International Group
Overview As an FPGA Engineer at Susquehanna, you will sit at the cusp of hardware and trading and help us as we continue to build some of the industry's most cutting edge ultra-low latency trading environments. As one of the world's largest market makers, Susquehanna was one of the first high frequency trading firms to pioneer the use of hardware-accelerated trading systems. At Susquehanna, we don't believe in silos. We believe that people do their best work when they have the freedom to explor…
RTL Engineer (Ethernet)
Sivaltech is hiring an experienced RTL Design Engineer with strong Ethernet expertise for a high-performance Networking IC development role in San Jose, CA. Required Skills Strong RTL Design experience ( Verilog/SystemVerilog ) Hands-on with Ethernet (IEEE 802.3) Experience with MAC, PCS, PHY, SerDes integration Knowledge of ASIC/SoC design flow Experience in clock/reset/power domain design Exposure to Layer 2/3/4 protocols Experience with EDA tools (Synopsys, Cadence, Mentor) Preferred Experie…
DFT (Design for Test) Engineer.
Key Skills & Experience • Hands-on experience with the Siemens Tessent (Mentor Graphics) DFT tool suite. • Strong understanding of DFT fundamentals, including controllability, observability, scan insertion, and scan-based testing. • Expertise in ATPG (Automatic Test Pattern Generation), including pattern generation, analysis, debugging, and fault coverage improvement. • Experience with MBIST (Memory Built-In Self-Test), including memory test architecture, implementation, and diagnostics. • Good…
ASIC Design Team Lead with Security Clearance
Responsibilities Responsibilities - * The successful candidate is a recognized expert who designs, researches, and develops highly advanced applications supporting Arcfield's secure processing projects. * As such, you will lead a team of ASIC design engineers to create a design document that defines the chip's features, performance, and internal components. * You will finish developing, enhancing, and debugging the VHDL/Verifog for the chip. * This includes verifying the functionality of the de…